公开(公告)号：US20200083285A1

公开(公告)日：2020-03-12

申请号：US16352680

申请日：2019-03-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Toshihiko NAGASE ,  Daisuke WATANABE ,  Koji UEDA ,  Tadashi KAI ,  Kazumasa SUNOUCHI

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12 ,  H01F41/34

Abstract: According to one embodiment, a semiconductor storage device includes: a first memory cell and a second memory cell, each including a switching element and a resistance change element coupled to the switching element, and the first memory cell and the second memory cell being adjacent to each other; a non-active member having a switching function between the switching element of the first memory cell and the switching element of the second memory cell; and an insulator which covers at least one of an upper surface or a lower surface of the non-active member, a side surface of the non-active member, a side surface of the switching element of the first memory cell, and a side surface of the switching element of the second memory cell.

公开(公告)号：US20180269043A1

公开(公告)日：2018-09-20

申请号：US15704820

申请日：2017-09-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Koji UEDA ,  Koji YAMAKAWA ,  Toshihiko NAGASE ,  Youngmin EEH ,  Kazuya SAWADA

IPC: H01J37/34 ,  C23C14/35 ,  H01L21/02

CPC classification number: H01J37/3435 ,  C23C14/35 ,  C23C14/352 ,  C23C14/505 ,  C23C14/542 ,  H01J37/3405 ,  H01J37/3452 ,  H01L21/02175 ,  H01L21/02266 ,  H01L43/12

Abstract: According to one embodiment, a film formation method using a magnetron sputtering apparatus including first and second magnets provided on first and second target holders, includes forming an insulating film on a wafer placed on a main surface of a wafer stage by sputtering first and second insulating targets set on the first and second target holders, wherein the wafer includes an effective area to be used for a product and an ineffective area outside the effective area, and when viewed from a direction perpendicular to the main surface of the wafer stage, at least a part of the first magnet overlaps the effective area of the wafer placed on the main surface of the wafer stage, and the entire second magnet does not overlap the effective area of the wafer placed on the main surface of the wafer stage.

公开(公告)号：US20200303632A1

公开(公告)日：2020-09-24

申请号：US16566020

申请日：2019-09-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Daisuke WATANABE ,  Toshihiko NAGASE ,  Koji UEDA ,  Young Min EEH

IPC: H01L43/08 ,  G11C11/15 ,  H01F10/32 ,  H01L27/22 ,  H01F10/12 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16

Abstract: According to one embodiment, a magnetic device includes a magnetoresistive effect element. The magnetoresistive effect element includes a first nonmagnet, a second nonmagnet, a first ferromagnet between the first nonmagnet and the second nonmagnet, a third nonmagnet including a rare-earth oxide, the second nonmagnet between the first ferromagnet and the third nonmagnet, and a fourth nonmagnet between the second nonmagnet and the third nonmagnet and including a metal.

公开(公告)号：US20190088855A1

公开(公告)日：2019-03-21

申请号：US15918235

申请日：2018-03-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Koji YAMAKAWA ,  Koji UEDA

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32

Abstract: According to one embodiment, a magnetic memory device includes a lower region, and a stacked structure provided on the lower region, wherein the stacked structure includes a conductive oxide layer containing boron (B), a first magnetic layer provided between the lower region and the conductive oxide layer, having a variable magnetization direction, and containing iron (Fe) and boron (B), a second magnetic layer provided between the lower region and the first magnetic layer, having a fixed magnetization direction, and containing iron (Fe) and boron (B), and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer.

公开(公告)号：US20190079873A1

公开(公告)日：2019-03-14

申请号：US16186231

申请日：2018-11-09

Applicant: SK hynix Inc. ,  Toshiba Memory Corporation

Inventor： Yang-Kon KIM ,  Ki-Seon PARK ,  Bo-Mi LEE ,  Won-Joon CHOI ,  Guk-Cheon KIM ,  Daisuke WATANABE ,  Makoto NAGAMINE ,  Young-Min EEH ,  Koji UEDA ,  Toshihiko NAGASE ,  Kazuya SAWADA

IPC: G06F12/0875 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: An electronic device includes semiconductor memory, the semiconductor memory including an under layer; a first magnetic layer located over the under layer and having a variable magnetization direction; a tunnel barrier layer located over the first magnetic layer; and a second magnetic layer located over the tunnel barrier layer and having a pinned magnetization direction, wherein the under layer includes a first metal nitride layer having a NaCl crystal structure and a second metal nitride layer containing a light metal.