公开(公告)号：US11177135B2

公开(公告)日：2021-11-16

申请号：US16283570

申请日：2019-02-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuya Matsubara ,  Masayuki Kitamura ,  Atsuko Sakata

IPC: H01L21/3065 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3213

Abstract: A mask member contains tungsten (W), boron (B), and carbon (C). The mask member includes a first portion in contact with a process film, the first portion, in which the terms of the composition ratio, which correspond to boron and carbon, are larger than the term of the composition ratio, which corresponds to tungsten, and a second portion in which the term of the composition ratio, which corresponds to tungsten, is larger than the terms of the composition ratio, which correspond to carbon and boron.

公开(公告)号：US10164180B2

公开(公告)日：2018-12-25

申请号：US15704802

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Hiromichi Kuriyama ,  Yuya Matsubara ,  Kazunori Harada ,  Takuya Hirohashi ,  Harumi Seki ,  Masumi Saitoh

IPC: G11C11/00 ,  H01L45/00 ,  G11C13/00

Abstract: According to one embodiment, a variable resistance element includes first and second conductive layers and a first layer. The first conductive layer includes at least one of silver, copper, zinc, titanium, vanadium, chrome, manganese, iron, cobalt, nickel, tellurium, or bismuth. The second conductive layer includes at least one of platinum, gold, iridium, tungsten, palladium, rhodium, titanium nitride, or silicon. The first layer includes oxygen and silicon and is provided between the first conductive layer and the second conductive layer. The first layer includes a plurality of holes. The holes are smaller than a thickness of the first layer along a first direction. The first direction is from the second conductive layer toward the first conductive layer. The first layer does not include carbon, or a composition ratio of carbon included in the first layer to silicon included in the first layer is less than 0.1.

公开(公告)号：US09754793B2

公开(公告)日：2017-09-05

申请号：US15376336

申请日：2016-12-12

Applicant: Toshiba Memory Corporation

Inventor： Shinichi Nakao ,  Shunsuke Ochiai ,  Yusuke Oshiki ,  Kei Watanabe ,  Mitsuhiro Omura ,  Kosuke Horibe ,  Atsuko Sakata ,  Junichi Wada ,  Soichi Yamazaki ,  Masayuki Kitamura ,  Yuya Matsubara

IPC: H01L21/336 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/11582

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11582 ,  H01L28/00

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.