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    Method of forming a semiconductor device having a metal layer
    1.
    发明申请
    Method of forming a semiconductor device having a metal layer 有权
    形成具有金属层的半导体器件的方法

    公开(公告)号：US20060063364A1

    公开(公告)日：2006-03-23

    申请号：US10943383

    申请日：2004-09-17

    申请人： Tab Stephens ,  Brian Goolsby ,  Bich-Yen Nguyen ,  Voon-Yew Thean

    发明人： Tab Stephens ,  Brian Goolsby ,  Bich-Yen Nguyen ,  Voon-Yew Thean

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28088 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/785 ,  Y10S438/963

    摘要： A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.

    摘要翻译： 在金属氧化物之上形成金属层，其中在半导体衬底上形成金属氧化物。 确定金属层的预定临界尺寸。 执行第一蚀刻以将金属层向下蚀刻到金属氧化物并在金属层的侧壁处形成基脚。 用于移除基脚以靶向预定临界尺寸的第二蚀刻，其中第二蚀刻对金属氧化物是选择性的。 在一个实施例中，在金属层上形成导电层。 可以蚀刻导电层的主体，留下与金属层接触的部分。 接下来，可以使用化学选择性地蚀刻与金属层接触的部分。

    SEMICONDUCTOR FABRICATION PROCESS INCLUDING RECESSED SOURCE/DRAIN REGIONS IN AN SOI WAFER
    2.
    发明申请
    SEMICONDUCTOR FABRICATION PROCESS INCLUDING RECESSED SOURCE/DRAIN REGIONS IN AN SOI WAFER 有权
    半导体制造工艺，包括SOI WAFER中的残留源/漏区

    公开(公告)号：US20060148196A1

    公开(公告)日：2006-07-06

    申请号：US11028811

    申请日：2005-01-03

    申请人： Voon-Yew Thean ,  Brian Goolsby ,  Bich-Yen Nguyen ,  Thien Nguyen ,  Tab Stephens

    发明人： Voon-Yew Thean ,  Brian Goolsby ,  Bich-Yen Nguyen ,  Thien Nguyen ,  Tab Stephens

    IPC分类号： H01L21/76

    CPC分类号： H01L29/66636 ,  H01L29/66772 ,  H01L29/78639

    摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.

    摘要翻译： 在绝缘体上硅（SOI）晶片中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构，其中隔离结构优选地延伸穿过有源层到BOX层的BOX层 晶圆。 去除有源层的上部以形成晶体管沟道结构。 在沟道结构上形成栅极电介质，在栅极电介质上形成栅极结构。 执行蚀刻通过栅介质，沟道结构和BOX层的暴露部分，然后从衬底体的暴露部分外延生长源极/漏极结构。 隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

    ELECTRONIC DEVICES INCLUDING A SEMICONDUCTOR LAYER
    3.
    发明申请
    ELECTRONIC DEVICES INCLUDING A SEMICONDUCTOR LAYER 有权
    包括半导体层的电子器件

    公开(公告)号：US20070272952A1

    公开(公告)日：2007-11-29

    申请号：US11836844

    申请日：2007-08-10

    申请人： Voon-Yew Thean ,  Brian Goolsby ,  Linda McCormick ,  Bich-Yen Nguyen ,  Colita Parker ,  Mariam Sadaka ,  Victor Vartanian ,  Ted White ,  Melissa Zavala

    发明人： Voon-Yew Thean ,  Brian Goolsby ,  Linda McCormick ,  Bich-Yen Nguyen ,  Colita Parker ,  Mariam Sadaka ,  Victor Vartanian ,  Ted White ,  Melissa Zavala

    IPC分类号： H01L29/80

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/1203

    摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

    摘要翻译： 电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。 在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。 在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。 可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。 可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。 在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

    Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit
    6.
    发明授权
    Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit 有权
    应变绝缘子集成电路中布局优化的选择性单轴应力松弛

    公开(公告)号：US07781277B2

    公开(公告)日：2010-08-24

    申请号：US11383113

    申请日：2006-05-12

    申请人： Bich-Yen Nguyen ,  Voon-Yew Thean

    发明人： Bich-Yen Nguyen ,  Voon-Yew Thean

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/0207 ,  H01L29/1033 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

    摘要： An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.

    摘要翻译： 集成电路包括NMOS和PMOS晶体管。 NMOS具有分别具有沿着第一和第二轴的第一和第二应力值的应变通道。 PMOS具有沿第一和第二轴具有第三和第四应力值的应变通道。 第一值应力与第三值不同，第二值与第四值不同。 NMOS和PMOS具有公共长度（L）和有效宽度（W），但扩散长度（SA）和/或源极/漏极（WS）的宽度不同。 NMOS WS可能超过PMOS WS。 NMOS可以包括位于栅极下方的有源层中的多个电介质结构。 PMOS的SA可以小于NMOS的SA。 集成电路可以包括氮化硅在NMOS上的拉伸应力源和在PMOS上的氮化硅的压应力。

    SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR
    7.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR 有权
    半导体器件结构及其方法

    公开(公告)号：US20070235807A1

    公开(公告)日：2007-10-11

    申请号：US11742955

    申请日：2007-05-01

    申请人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

    发明人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

    IPC分类号： H01L29/786

    CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66772

    摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

    摘要翻译： 在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。 衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。 底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。 然后在氧掺杂半导体层上外延生长半导体层。 在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。 然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。 不同类型的晶体管形成在不同的结晶取向上。

    Electronic device including semiconductor islands of different thicknesses over an insulating layer and a process of forming the same
    8.
    发明申请
    Electronic device including semiconductor islands of different thicknesses over an insulating layer and a process of forming the same 有权
    包括在绝缘层上具有不同厚度的半导体岛的电子器件及其形成方法

    公开(公告)号：US20070218707A1

    公开(公告)日：2007-09-20

    申请号：US11375893

    申请日：2006-03-15

    申请人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean

    发明人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean

    IPC分类号： H01L21/31

    CPC分类号： H01L21/32 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/84

    摘要： A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.

    摘要翻译： 形成电子器件的方法可以包括在覆盖在衬底上的半导体层上形成图案化的抗氧化层，并且图案化半导体层以形成半导体岛。 半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。 该方法还可以包括沿着半导体岛的一侧形成耐氧化材料或者沿半导体岛的一侧选择性地沉积半导体材料。 该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛， 并将抗氧化材料转化为含氧环境。

    Electronic devices including a semiconductor layer and a process for forming the same
    9.
    发明授权
    Electronic devices including a semiconductor layer and a process for forming the same 有权
    包括半导体层的电子器件及其形成方法

    公开(公告)号：US07265004B2

    公开(公告)日：2007-09-04

    申请号：US11273092

    申请日：2005-11-14

    申请人： Voon-Yew Thean ,  Brian J. Goolsby ,  Linda B. McCormick ,  Bich-Yen Nguyen ,  Colita M. Parker ,  Mariam G. Sadaka ,  Victor H. Vartanian ,  Ted R. White ,  Melissa O. Zavala

    发明人： Voon-Yew Thean ,  Brian J. Goolsby ,  Linda B. McCormick ,  Bich-Yen Nguyen ,  Colita M. Parker ,  Mariam G. Sadaka ,  Victor H. Vartanian ,  Ted R. White ,  Melissa O. Zavala

    IPC分类号： H01L21/84

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/1203

    摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

    摘要翻译： 电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。 在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。 在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。 可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。 可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。 在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。