公开(公告)号：US4714965A

公开(公告)日：1987-12-22

申请号：US807745

申请日：1985-12-11

申请人： Tadaaki Yoshinaka ,  Takao Inoue ,  Kazuo Tomita

发明人： Tadaaki Yoshinaka ,  Takao Inoue ,  Kazuo Tomita

IPC分类号： H04N5/956 ,  H04N5/95 ,  H04N9/81 ,  H04N9/86 ,  H04N9/89 ,  H04N9/896 ,  H04N5/78 ,  H04N5/85

CPC分类号： H04N9/896

摘要： In a time base corrector for correcting time base fluctuations of signals reproduced from a record medium, on which a plurality of time-compressed component signals occurring within one horizontal period in a predetermined sequential order are recorded in response to a clock signal with a predetermined frequency, a write clock pulse generator used in the time base corrector includes a phase shifter for shifting the phase of an incoming write clock signal, whereby the write clock signal having a frequency different from the predetermined frequency is generated in response to a horizontal synchronizing signal, the start time of each of the plurality of reproduced component signals is detected and the shifting amount of the write clock signal by the phase shifter is switched in accordance with the detected output so as to synchronize the write clock signal with the start time of each of the reproduced component signal.

摘要翻译： 在用于校正从记录介质再现的信号的时基波动的时基校正器中，响应于具有预定频率的时钟信号来记录以预定顺序次序在一个水平周期内出现的多个时间压缩分量信号 在时基校正器中使用的写时钟脉冲发生器包括用于移位输入写时钟信号的相位的移相器，由此响应于水平同步信号产生具有与预定频率不同的频率的写时钟信号， 检测多个再现分量信号中的每一个的开始时间，并且根据检测到的输出切换由移相器写入的时钟信号的移位量，以使写入时钟信号与每个的时钟信号的开始时间同步 再现的分量信号。

公开(公告)号：US08330253B2

公开(公告)日：2012-12-11

申请号：US12107599

申请日：2008-04-22

申请人： Kazuo Tomita

发明人： Kazuo Tomita

IPC分类号： H01L23/544

CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.

摘要翻译： 本发明提供了一种用于提高半导体器件的可靠性的技术，其中即使在具有用作层间绝缘膜的低k膜的半导体器件中，即使在密封环切割时发生的裂纹扩展也可能受到限制。 在切割区域侧的每个层中形成虚拟过孔。 在俯视图中以矩阵形式，以相同的间隔形成虚拟通孔。 即使在切割时发生裂纹的情况下，也可以防止裂纹通过虚拟通孔扩散到密封环。 结果，可以提高在电路形成区域中吸收的水分的耐受性，并且可以防止可靠性的劣化。

公开(公告)号：US08093149B2

公开(公告)日：2012-01-10

申请号：US12183795

申请日：2008-07-31

申请人： Kazuo Tomita

发明人： Kazuo Tomita

IPC分类号： H01L21/4763

CPC分类号： H01L23/3192 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer and a manufacturing method for a semiconductor device are provided, which prevent peeling-off of films and pattern skipping in a wafer edge portion. A silicone substrate has formed thereon gate structures in active regions isolated by a trench isolation film; a contact interlayer film; and a multilayer interconnection structure formed by alternate laminations of low-k via interlayer films, i.e., V layers, and low-k interconnect interlayer films, i.e., M layers. In a Fine layer ranging from first to fifth interlayer films, the M layers are removed from the wafer edge portion, but the V layers are not removed therefrom. Further, the contact interlayer film is not removed from the wafer edge portion.

摘要翻译： 提供半导体晶片和半导体器件的制造方法，其防止膜的剥离和晶片边缘部分中的图案跳过。 在其上形成有硅衬底，其中沟槽隔离膜隔离的有源区中有栅极结构; 接触层间膜; 以及通过层间薄膜即V层和低k互连层间膜（即M层）的交替叠层形成的多层互连结构。 在从第一到第五层间膜的细层中，从晶片边缘部分去除M层，但不从其去除V层。 此外，接触层间膜不从晶片边缘部分移除。

公开(公告)号：US07825489B2

公开(公告)日：2010-11-02

申请号：US12265454

申请日：2008-11-05

申请人： Kazuo Tomita

发明人： Kazuo Tomita

IPC分类号： H01L29/00

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.

公开(公告)号：US20060289997A1

公开(公告)日：2006-12-28

申请号：US11455699

申请日：2006-06-20

申请人： Kazuo Tomita

发明人： Kazuo Tomita

IPC分类号： H01L23/52

CPC分类号： H01L23/5329 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/562 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05554 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042

摘要： The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part.

公开(公告)号：US06756691B2

公开(公告)日：2004-06-29

申请号：US10080683

申请日：2002-02-25

申请人： Kazuo Tomita ,  Atsushi Ueno

发明人： Kazuo Tomita ,  Atsushi Ueno

IPC分类号： H01L23544

CPC分类号： H01L22/34 ,  H01L23/544 ,  H01L27/10805 ,  H01L27/10852 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A mark structure (100) consists of a gate oxide film (102) formed on a semiconductor substrate (101), a gate wiring layer (103) formed on the gate oxide film (102), an insulating film (104) formed on the gate wiring layer (103) and a sidewall (105) formed in contact with side surfaces of the insulating film (104), the gate wiring layer (103) and the gate oxide film (102). An opaque bit line layer (113) is formed of a polycide consisting of a doped polysilicon layer (1131) and a tungsten silicide layer (1132), extending from on the interlayer insulating film (107) to on the mark structure (100). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.

摘要翻译： 标记结构（100）由形成在半导体衬底（101）上的栅极氧化膜（102），形成在栅极氧化膜（102）上的栅极布线层（103），形成在栅极氧化膜上的绝缘膜 栅极布线层（103）和与绝缘膜（104），栅极布线层（103）和栅极氧化膜（102）的侧面接触形成的侧壁（105）。 不透明位线层（113）由从层间绝缘膜（107）延伸到标记结构（100）上的掺杂多晶硅层（1131）和硅化钨层（1132）组成的多晶硅化物形成。 利用这种结构，在光刻工艺中能够以高精度测量对准标记和覆盖检查标记的半导体器件不需要标记的结构，并且抑制在制造半导体器件的过程中产生外来物质以防止劣化 可以提供制造工艺成品率和制造半导体器件的方法。

公开(公告)号：US5963384A

公开(公告)日：1999-10-05

申请号：US979208

申请日：1997-11-26

申请人： Minoru Kawahara ,  Hitoshi Tsujii ,  Kazuo Tomita

发明人： Minoru Kawahara ,  Hitoshi Tsujii ,  Kazuo Tomita

IPC分类号： G11B5/09 ,  G11B5/008 ,  G11B5/02 ,  G11B5/53 ,  G11B15/087 ,  G11B5/03 ,  G11B15/14

CPC分类号： G11B15/087 ,  G11B5/0086 ,  G11B5/53

摘要： A signal recording device is provided for transmitting recording data signals via a rotary transformer to a rotary drum having a rotary head for recording data so that control data may be transmitted in a shorter time period and resolution along the time axis may be improved. A 1-bit start bit SB and 2-bit mode setting bits PD are followed by 3-bit group bits GP and 3-bit channel bits CL for a single bit mode, by 3-bit group bits GP and an 8-bit bit patterns BP for a multi-bit mode and by a 4-bit channel number DAN and 8-bit data DAD for D/A data. An even parity PE is appended for each of the respective modes. A continuation flag CF is further appended for the single-bit mode and the multi-bit mode.

摘要翻译： 提供一种信号记录装置，用于通过旋转变压器将记录数据信号传送到具有用于记录数据的旋转磁头的旋转磁鼓，从而可以在更短的时间内传输控制数据，并且可以提高沿着时间轴的分辨率。 1位起始位SB和2位模式设置位PD后面是3位组位GP和3位通道位CL，用于单位模式，3位组位GP和8位位 用于多位模式的模式BP和用于D / A数据的4位通道数DAN和8位数据DAD。 对于各个模式中的每一个，附加偶校验PE。 对于单位模式和多位模式，还附加连续标志CF。

公开(公告)号：US4116184A

公开(公告)日：1978-09-26

申请号：US757013

申请日：1977-01-05

申请人： Kazuo Tomita

发明人： Kazuo Tomita

IPC分类号： F02D35/00 ,  F02M25/08 ,  F02M23/12

CPC分类号： F02D35/00 ,  F02M25/089

摘要： An apparatus for treating evaporated fuel gas from a fuel tank of a motor vehicle having an internal combustion engine. The fuel treating apparatus includes a means for sensing the amount of fuel gas vapors in the fuel tank, a means for drawing the fuel vapors into the intake of the engine and a means for varying the air/fuel ratio in the intake of the engine in response to the amount of fuel gas vapors sensed in the fuel tank by the sensing means whereby a rich air/fuel mixture in the intake of the engine is prevented.

摘要翻译： 一种用于处理来自具有内燃机的机动车辆的燃料箱的蒸发燃料气体的装置。 燃料处理装置包括用于感测燃料箱中的燃料气体蒸气量的装置，用于将燃料蒸汽抽吸到发动机的进气口中的装置和用于改变发动机进气中的空气/燃料比的装置 响应于通过感测装置在燃料箱中感测的燃料气体蒸气的量，从而防止发动机的进气中的富空气/燃料混合物。

公开(公告)号：US20110237070A1

公开(公告)日：2011-09-29

申请号：US13074899

申请日：2011-03-29

申请人： Kazumasa YONEKURA ,  Kazuo Tomita

发明人： Kazumasa YONEKURA ,  Kazuo Tomita

IPC分类号： H01L21/768

CPC分类号： H01L21/76835 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor device is provided which can precisely control the depth of a wiring trench pattern, and which can suppress the damage on the wiring trench pattern. A second low dielectric constant film, a third low dielectric constant film, and a film for serving as a mask layer are laminated over a diffusion preventing film in that order. The film for serving as the mask layer is etched, and a wiring trench pattern is formed which has its bottom made of a surface of the third low dielectric constant film, so that a mask layer is formed. A first resist mask is removed by asking. A wiring trench is formed using the wiring trench pattern of the mask layer such that a bottom of the trench is comprised of the second low dielectric constant film. A layer from a top surface of the copper metal to the third low dielectric constant film is removed by a CMP method. Each low dielectric constant film has a dielectric constant lower than that of FSG, and the second low dielectric constant film has the dielectric constant lower than that of the third low dielectric constant film.

摘要翻译： 提供一种半导体器件的制造方法，其可以精确地控制布线沟槽图案的深度，并且可以抑制对布线沟槽图案的损坏。 将第二低介电常数膜，第三低介电常数膜和用作掩模层的膜按顺序层叠在扩散防止膜上。 蚀刻用作掩模层的膜，并且形成其底部由第三低介电常数膜的表面制成的布线沟槽图案，从而形成掩模层。 第一个抗蚀剂掩模通过询问被去除。 使用掩模层的布线沟槽图形形成布线沟槽，使得沟槽的底部由第二低介电常数膜构成。 通过CMP方法去除从铜金属的顶表面到第三低介电常数膜的层。 每个低介电常数膜的介电常数低于FSG，而第二低介电常数膜的介电常数低于第三低介电常数膜。

公开(公告)号：US20090032847A1

公开(公告)日：2009-02-05

申请号：US12183795

申请日：2008-07-31

申请人： Kazuo Tomita

发明人： Kazuo Tomita

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L23/3192 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer and a manufacturing method for a semiconductor device are provided, which prevent peeling-off of films and pattern skipping in a wafer edge portion. A silicone substrate has formed thereon gate structures in active regions isolated by a trench isolation film; a contact interlayer film; and a multilayer interconnection structure formed by alternate laminations of low-k via interlayer films, i.e., V layers, and low-k interconnect interlayer films, i.e., M layers. In a Fine layer ranging from first to fifth interlayer films, the M layers are removed from the wafer edge portion, but the V layers are not removed therefrom. Further, the contact interlayer film is not removed from the wafer edge portion.

摘要翻译： 提供半导体晶片和半导体器件的制造方法，其防止膜的剥离和晶片边缘部分中的图案跳过。 在其上形成有硅衬底，其中沟槽隔离膜隔离的有源区中有栅极结构; 接触层间膜; 以及通过层间薄膜即V层和低k互连层间膜（即M层）的交替叠层形成的多层互连结构。 在从第一到第五层间膜的细层中，从晶片边缘部分去除M层，但不从其去除V层。 此外，接触层间膜不从晶片边缘部分移除。