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公开(公告)号：US20060104413A1
公开(公告)日：2006-05-18
申请号：US10548287
申请日：2004-03-02
CPC分类号： G03F7/70425 , G03F7/70291 , G03F7/70358 , G03F7/70433 , G03F7/70441 , G03F7/70466 , G03F7/70475 , G03F7/70866
摘要： A mask repeater for transferring the pattern of a master mask onto a real mask by exposure and transferring the pattern on the real mask onto a substrate such as a semiconductor wafer. The size of the master mask is larger than that of the real mask. By using an optical system for reduction-projecting soft X-rays, a 1:1 magnification mask, which is the next generation mask, is fabricated. In a scan exposure system, the shape of a slit used for scanning is made fixed, and exposure is conducted only for the exposed region to realize oblique exposure. When the shape of the slit is a trapezoid and when the exposed region is reciprocated in the scanning direction, the number of joint exposures can be decreased.
摘要翻译： 一种掩模中继器，用于通过曝光将主掩模的图案转印到真实掩模上，并将真实掩模上的图案转印到诸如半导体晶片的基板上。 主掩模的尺寸大于真面罩的尺寸。 通过使用用于还原投射软X射线的光学系统，制造作为下一代掩模的1：1放大掩模。 在扫描曝光系统中，用于扫描的狭缝的形状被固定，并且仅对曝光区域进行曝光以实现倾斜曝光。 当狭缝的形状是梯形时，并且当暴露区域沿扫描方向往复运动时，可以减少关节暴露的次数。
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公开(公告)号：US07663734B2
公开(公告)日：2010-02-16
申请号：US10552731
申请日：2004-04-09
IPC分类号： G03B27/54
CPC分类号： G03F7/70425 , G03F7/70291 , G03F7/70358 , G03F7/70433 , G03F7/70441 , G03F7/70466 , G03F7/70866
摘要： In a pattern writing method for writing a pattern on a substrate by the use of projection patterns output from a mirror device including two-dimensionally arranged micromirrors, exposure is implemented by ON/OFF controlling each micromirror and partly overlapping the projection patterns from the mirror device at least in a one-dimensional direction, thereby accurately controlling the exposure of intermediate amounts of light.
摘要翻译： 在通过使用从包括二维布置的微镜的反射镜装置输出的投影图案在基板上写入图案的图案写入方法中，通过对每个微反射镜进行ON / OFF控制来实现曝光，并且部分地与来自反射镜装置的投影图案重叠 至少在一维方向上，从而精确地控制中等量的光的曝光。
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公开(公告)号：US20060147841A1
公开(公告)日：2006-07-06
申请号：US10552731
申请日：2004-04-09
IPC分类号： G03C5/00
CPC分类号： G03F7/70425 , G03F7/70291 , G03F7/70358 , G03F7/70433 , G03F7/70441 , G03F7/70466 , G03F7/70866
摘要： In a pattern writing method for writing a pattern on a substrate by the use of projection patterns output from a mirror device including two-dimensionally arranged micromirrors, exposure is implemented by ON/OFF controlling each micromirror and partly overlapping the projection patterns from the mirror device at least in a one-dimensional direction, thereby accurately controlling the exposure of intermediate amounts of light.
摘要翻译： 在通过使用从包括二维布置的微镜的反射镜装置输出的投影图案在基板上写入图案的图案写入方法中，通过对每个微反射镜进行ON / OFF控制来实现曝光，并且部分地与来自反射镜装置的投影图案重叠 至少在一维方向上，从而精确地控制中等量的光的曝光。
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公开(公告)号：US20060252160A1
公开(公告)日：2006-11-09
申请号：US10567828
申请日：2004-08-09
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/20 , H01J37/3174
摘要： A 1:1 mask and a wafer are arranged so as to be vertical. Thus, a pattern portion of the 1:1 mask does not warp at all and, therefore, even when the mask has no beam, it is not necessary to strongly stretch a pattern portion thereof. Further, a gap between the mask and the wafer can be further reduced. Since it is not necessary to strongly stretch the pattern portion of the stencil mask, a very thin membrane can be bonded to the pattern portion. Thus, even when the acceleration voltage of an electron beam is as low as several kV, it is possible to use a mask called a membrane mask and carry out pattern formation by one-time exposure even in the case of a doughnut-shaped pattern.
摘要翻译： 1：1掩模和晶片布置成垂直。 因此，1：1掩模的图案部分根本不翘曲，因此即使当掩模没有光束时，也不需要强烈地拉伸图案部分。 此外，可以进一步减小掩模和晶片之间的间隙。 由于不需要强力地拉伸模板掩模的图案部分，所以可以将非常薄的膜结合到图案部分。 因此，即使当电子束的加速电压低至几kV时，也可以使用称为膜掩模的掩模，并且即使在环形图案的情况下也可以通过一次曝光进行图案形成。
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公开(公告)号：US07474383B2
公开(公告)日：2009-01-06
申请号：US10543454
申请日：2004-01-28
CPC分类号： G03F7/70283 , G03F7/70291
摘要： Laser light in a pattern reflected by a two-dimensional array micromirror 106 that is controlled on the basis of mask data of a mask pattern data output device 107 forms an enlarged pattern 110. This enlarged pattern is projected in a reduced manner onto a mask substrate 109 through a reduction-projection optical system 102, thereby forming a lithography pattern 111. Since a large number of patterns are written in an instant by the two-dimensional array micromirror 106, a time required for lithography the entire mask pattern is extremely shortened as compared with a conventional one. As a result, the mask cost can be largely reduced.
摘要翻译： 由基于掩模图案数据输出装置107的掩模数据控制的由二维阵列微镜106反射的图案的激光形成放大图案110.该放大图案以减小的方式投影到掩模基板上 通过缩小投影光学系统102，从而形成光刻图案111.由于通过二维阵列微镜106瞬时写入大量图案，因此平版印刷整个掩模图案所需的时间被极大地缩短为 与传统的相比。 结果，掩模成本可以大大降低。
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公开(公告)号：US08183670B2
公开(公告)日：2012-05-22
申请号：US11651034
申请日：2007-01-09
IPC分类号： H01L29/04
CPC分类号： H01L21/3185 , H01L21/30604 , H01L21/31654 , H01L21/318 , H01L29/6659
摘要： In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
摘要翻译： 在形成在具有大致（110）晶面取向的硅表面上的半导体器件中，硅表面变平，使得表面Ra的算术平均偏差不大于0.15nm，优选为0.09nm，这使得能够制造 高迁移率的n-MOS晶体管。 通过在脱氧H 2 O或低OH密度气氛中清洗硅表面，通过在氧自由基气氛中重复自牺牲氧化物膜的沉积工艺和自牺牲氧化物膜的去除工艺来获得这种扁平化的硅表面 ，或通过氢或重氢强烈地终止硅表面。 自牺牲氧化膜的沉积工艺可以通过各向同性氧化进行。
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公开(公告)号：US07566936B2
公开(公告)日：2009-07-28
申请号：US11606181
申请日：2006-11-30
申请人： Tadahiro Ohmi , Koji Kotani , Shigetoshi Sugawa
发明人： Tadahiro Ohmi , Koji Kotani , Shigetoshi Sugawa
IPC分类号： H01L29/76
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823821 , H01L27/092 , H01L27/0922 , H01L29/66795 , H01L29/7851
摘要： A CMOS device includes a p-channel MOS transistor and an n-channel MOS transistor having a structure formed on a (100) surface of a silicon substrate and having a different crystal surface, a high-quality gate insulation film formed on such a structure by a microwave plasma process, and a gate electrode formed thereon, wherein the size and the shape of the foregoing structure is set such that the carrier mobility is balanced between the p-channel MOS transistor and the n-channel MOS transistor.
摘要翻译： CMOS器件包括具有形成在硅衬底（100）表面上并具有不同晶体表面的结构的p沟道MOS晶体管和n沟道MOS晶体管，形成在这种结构上的高质量栅极绝缘膜 通过微波等离子体处理和形成在其上的栅电极，其中上述结构的尺寸和形状被设置为使得载流子迁移率在p沟道MOS晶体管和n沟道MOS晶体管之间平衡。
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8.发明申请公开(公告)号：US20080224145A1
公开(公告)日：2008-09-18
申请号：US11907348
申请日：2007-10-11
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Katsuyuki Sekine , Yuji Saito
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Katsuyuki Sekine , Yuji Saito
IPC分类号： H01L29/04 , H01L29/788 , H01L29/78 , H01L27/12 , H01L21/316 , H01L21/762
CPC分类号： H01L21/28185 , G11C11/16 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28238 , H01L21/28291 , H01L27/11521 , H01L27/11585 , H01L27/1159 , H01L27/1203 , H01L29/045 , H01L29/4908 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/7833 , H01L29/78603 , H01L29/78612 , H01L29/7883
摘要： A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.
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公开(公告)号：US20070105523A1
公开(公告)日：2007-05-10
申请号：US10560703
申请日：2004-06-11
CPC分类号： H01L21/82385 , H01L21/823807 , H01L27/092 , H01L29/785 , H03F1/26 , H03F2200/372 , H03G1/0029 , H03G1/007
摘要： A low noise amplifier is assumed to comprise an MIS transistor and to amplify an input signal keeping noise at a low level, and the MIS transistor comprises a semiconductor substrate for comprising a first crystal plane as a principal plane, a semiconductor structure, formed as a part of the semiconductor substrate, for comprising a pair of sidewall planes defined by the second crystal plane different from the first crystal plane and a top plane defined by the third crystal plane different from the second crystal plane, a gate insulator of uniform thickness covering the principal plane, the sidewall planes and the top plane, a gate electrode for continuously covering the principal plane, the sidewall planes and the top plane on top of the gate insulator, and a single conductivity type diffusion area formed in the region to either side of the gate electrode in the semiconductor substrate and the semiconductor structure and continuously extending along the principal plane, the sidewall planes and the top plane. Such a configuration allows significant reduction of the 1/f noise and the signal distortion applied to an output signal by the low noise amplifier and therefore a circuit for compensating for the reduction of the amplitude is no longer of necessity, allowing reduction in size.
摘要翻译： 假设低噪声放大器包括MIS晶体管并且将保持噪声保持在低电平的输入信号放大，并且MIS晶体管包括用于包括第一晶面作为主平面的半导体衬底，形成为 所述半导体衬底的一部分包括由不同于所述第一晶体面的所述第二晶体面限定的一对侧壁平面和由与所述第二晶体面不同的所述第三晶体面限定的顶面，覆盖所述半导体衬底的均匀厚度的栅极绝缘体 主平面，侧壁平面和顶面，用于连续覆盖主平面，侧壁平面和栅极绝缘体顶部的顶面的栅极，以及在该区域中形成的单一导电型扩散区域 半导体衬底中的栅电极和半导体结构，并且沿着主平面连续延伸，侧壁p 车道和顶层飞机。 这样的配置允许显着降低由低噪声放大器施加到输出信号的1 / f噪声和信号失真，因此不再需要用于补偿幅度减小的电路，从而允许尺寸减小。
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10.发明申请公开(公告)号：US20060180840A1
公开(公告)日：2006-08-17
申请号：US10560397
申请日：2004-06-11
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/66787 , H01L21/823807 , H01L21/82385 , H01L27/092
摘要： A rectangular parallelepiped projecting portion (21) having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion (21), thereby generating a MOS transistor. By connecting in parallel a p-channel MOS transistor and an n-channel MOS transistor produced as described above, a switch of a switched capacitor circuit is configured, thereby reducing a leak current and a DC offset of the switched capacitor circuit.
摘要翻译： 在硅衬底上形成具有H B高度和W B B的宽度的长方体的突出部分（21），并且栅极氧化膜形成在 突出部分（21）的顶表面和侧表面的一部分，从而产生MOS晶体管。 通过并联连接如上所述制造的p沟道MOS晶体管和n沟道MOS晶体管，构造开关电容器电路的开关，从而减小开关电容器电路的漏电流和DC偏移。
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