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    Semiconductor integrated circuit device with operation/function setting information memory
    2.
    发明授权
    Semiconductor integrated circuit device with operation/function setting information memory 失效
    具有操作/功能设定信息存储器的半导体集成电路器件

    公开(公告)号：US06700817B2

    公开(公告)日：2004-03-02

    申请号：US10265728

    申请日：2002-10-08

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    IPC分类号： G11C1604

    CPC分类号： G11C5/143 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/26 ,  G11C16/30

    摘要： A semiconductor integrated circuit device includes a nonvolatile memory cell, a source of the cell receiving a ground potential, and a gate of the cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the cell, and a gate of the transistor receiving a second control signal; and a controller. The controller receives a third control signal generated upon detection of power-on and outputs the first and second control signals. A potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.

    摘要翻译： 半导体集成电路装置包括：非易失性存储单元，接收地电位的单元的源极和接收第一控制信号的单元的栅极; 晶体管，晶体管的源极，接收所述单元的漏极电位，以及所述晶体管的栅极接收第二控制信号; 和控制器。 控制器接收在检测到电源接通时产生的第三控制信号，并输出第一和第二控制信号。 第一控制信号的电位从接地电位变化到在第一时间段期间保持的接地电位不同的电位，并且第二控制信号的电位从地电势变为不同于 地电位，在第二段时间内保持。

    Semiconductor integrated circuit device
    3.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06320428B1

    公开(公告)日：2001-11-20

    申请号：US09527582

    申请日：2000-03-17

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    IPC分类号： H03K522

    CPC分类号： G11C5/143 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/26 ,  G11C16/30

    摘要： A semiconductor integrated circuit device has a data storage section for storing mode setting data corresponding to products of a plurality of types, redundancy data, and so on. The redundancy storage section is made up of a nonvolatile transistor for storing the mode setting data corresponding to the products, the redundancy data, etc., a latch circuit for latching data read out from the nonvolatile transistor and generating a mode signal, and a transmission gate for transmitting the data from read out from the nonvolatile transistor to the latch circuit. The semiconductor integrated circuit device also has an internal voltage generator for generating an internal voltage. This internal voltage is used as the power supply voltage of the data storage section.

    摘要翻译： 半导体集成电路装置具有用于存储对应于多种类型，冗余数据等的产品的模式设置数据的数据存储部分。 冗余存储部分由用于存储对应于产品，冗余数据等的模式设置数据的非易失性晶体管，用于锁存从非易失性晶体管读出的数据并产生模式信号的锁存电路，以及传输 用于将从非易失性晶体管读出的数据发送到锁存电路。 半导体集成电路器件还具有用于产生内部电压的内部电压发生器。 该内部电压用作数据存储部分的电源电压。

    Semiconductor integrated circuit device
    4.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US6052313A

    公开(公告)日：2000-04-18

    申请号：US030915

    申请日：1998-02-26

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    IPC分类号： G11C5/00 ,  G11C5/14 ,  G11C16/04 ,  H01L29/78 ,  H03K5/153 ,  H03K5/22

    CPC分类号： G11C5/143 ,  G11C16/30 ,  G11C7/1045 ,  G11C16/26 ,  G11C5/14

    摘要： A semiconductor integrated circuit device has a data storage section for storing mode setting data corresponding to products of a plurality of types, redundancy data, and so on. The redundancy storage section is made up of a nonvolatile transistor for storing the mode setting data corresponding to the products, the redundancy data, etc., a latch circuit for latching data read out from the nonvolatile transistor and generating a mode signal, and a transmission gate for transmitting the data from read out from the nonvolatile transistor to the latch circuit. The semiconductor integrated circuit device also has an internal voltage generator for generating an internal voltage. This internal voltage is used as the power supply voltage of the data storage section.

    摘要翻译： 半导体集成电路装置具有用于存储对应于多种类型，冗余数据等的产品的模式设置数据的数据存储部分。 冗余存储部分由用于存储对应于产品，冗余数据等的模式设置数据的非易失性晶体管，用于锁存从非易失性晶体管读出的数据并产生模式信号的锁存电路，以及传输 用于将从非易失性晶体管读出的数据发送到锁存电路。 半导体集成电路器件还具有用于产生内部电压的内部电压发生器。 该内部电压用作数据存储部分的电源电压。

    Semiconductor integrated circuit device with erasable and programmable fuse memory
    5.
    发明授权
    Semiconductor integrated circuit device with erasable and programmable fuse memory 失效
    具有可擦除和可编程保险丝存储器的半导体集成电路器件

    公开(公告)号：US06856543B2

    公开(公告)日：2005-02-15

    申请号：US10743385

    申请日：2003-12-23

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    IPC分类号： G11C5/00 ,  G11C5/14 ,  G11C16/04 ,  H01L29/78 ,  H03K5/153 ,  H03K5/22

    CPC分类号： G11C5/143 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/26 ,  G11C16/30

    摘要： A semiconductor integrated circuit device includes fuse cells arranged at a fuse cell array, a fuse cell data program and erase circuit, a fuse cell data control circuit, and fuse data latch circuits. The fuse cells include erasable and programmable nonvolatile memory cells. The fuse cell data program and erase circuit programs fuse data to the memory cells and erases the fuse data from the memory cells. The fuse cell data control circuit controls read out timing of the fuse data stored in the memory cells based on a signal generated upon detection of power-on. The fuse data latch circuits latch the fuse data read out from the memory cells.

    摘要翻译： 半导体集成电路器件包括设置在熔丝单元阵列处的熔丝单元，熔丝单元数据程序和擦除电路，熔丝单元数据控制电路和熔丝数据锁存电路。 熔丝单元包括可擦除和可编程的非易失性存储单元。 熔丝单元数据程序和擦除电路程序将数据熔化到存储单元，并从存储单元擦除熔丝数据。 熔丝单元数据控制电路基于在检测到通电时产生的信号来控制存储在存储单元中的熔丝数据的读出定时。 熔丝数据锁存电路锁存从存储器单元读出的熔丝数据。

    Power supply circuit and semiconductor memory device having the same
    9.
    发明授权
    Power supply circuit and semiconductor memory device having the same 有权

    公开(公告)号：US06356499B1

    公开(公告)日：2002-03-12

    申请号：US09640370

    申请日：2000-08-17

    申请人： Hironori Banba ,  Shigeru Atsumi

    发明人： Hironori Banba ,  Shigeru Atsumi

    IPC分类号： G11C700

    CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/073

    摘要： A number of booster circuits to be operated out of a plurality of booster circuits are selected in accordance with a level of the boosted voltage to be provided at a common voltage output terminal of the plurality of booster circuits. With such an arrangement, fluctuations in the output voltage that can appear when a light load is applied to the voltage output terminal of the booster circuits can be effectively reduced to make the semiconductor memory device driven by the power supply circuit operate reliably. Further, one of the output terminals of intermediate voltage booster circuits is connected to the output terminal of a high voltage booster circuit. Then, a desired voltage can be obtained from the booster circuits that are implemented without using costly transistors to reduce the chip cost.

    Booster circuit and semiconductor memory device having the same
    10.
    发明授权
    Booster circuit and semiconductor memory device having the same 有权
    具有相同功能的升压电路和半导体存储器件

    公开(公告)号：US06195307B1

    公开(公告)日：2001-02-27

    申请号：US09502045

    申请日：2000-02-11

    申请人： Akira Umezawa ,  Shigeru Atsumi ,  Hironori Banba

    发明人： Akira Umezawa ,  Shigeru Atsumi ,  Hironori Banba

    IPC分类号： G11C700

    CPC分类号： G11C5/145 ,  G11C16/30

    摘要： In a booster circuit, a gate of an input-side transistor whose end is supplied with a power supply voltage is supplied with an inverted signal of a signal supplied to a signal input terminal of a booster unit at a first stage or supplied with an AND signal of the inverted signal and a booster circuit activation signal. Therefore, when the transistor at the first stage operates, the input-side transistor is turned off. Accordingly, a back flow of a current from inside the booster circuit to a power supply is prevented, so that the efficiency of the booster circuit can be improved. Further, fluctuations of the output voltage are not brought about even when the power supply voltage greatly fluctuates, so that the reliability of peripheral elements and memory cells can be improved and the allowable range of an external power supply voltage can be widened.

    摘要翻译： 在升压电路中，向其端部供给电源电压的输入侧晶体管的栅极提供在第一级提供给增压器单元的信号输入端子的信号的反相信号，或者被提供有“ 反相信号的信号和升压电路激活信号。 因此，当第一级的晶体管工作时，输入侧晶体管截止。 因此，防止了从升压电路内部到电源的电流的反向流动，从而可以提高升压电路的效率。 此外，即使当电源电压剧烈波动时也不会产生输出电压的波动，从而可以提高外围元件和存储单元的可靠性，并且可以扩大外部电源电压的允许范围。