公开(公告)号：US06525406B1

公开(公告)日：2003-02-25

申请号：US09687049

申请日：2000-10-13

申请人： Young Suk Chung ,  Sung Sik Jang ,  Jae Jin Lee ,  Tae Heon Lee ,  Hyung Ju Lee ,  Jung Woo Lee ,  Mu Hwan Seo ,  Jae Hak Yee ,  Ku Sun Hong

发明人： Young Suk Chung ,  Sung Sik Jang ,  Jae Jin Lee ,  Tae Heon Lee ,  Hyung Ju Lee ,  Jung Woo Lee ,  Mu Hwan Seo ,  Jae Hak Yee ,  Ku Sun Hong

IPC分类号： H01L23495

CPC分类号： H01L23/544 ,  H01L21/4842 ,  H01L23/3114 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a semiconductor package and a method for manufacturing the same. A planar or substantially planar die pad is disposed within a leadframe and is connected to the leadframe by a plurality of tie bars. An perimeter of an upper and lower surface of the die pad is half-etched to increase the moisture-permeation path of the finished package. A plurality of rectangular leads extends from the leadframe toward the die pad without contacting the die pad. A silver-plating layer may be formed on the upper surface of the leadframe. A semiconductor chip is mounted on the upper surface of the die pad in the leadframe. After deflashing, the package is treated with a sulfuric (H2SO4)-based solution to restore the internal leads to their original color. Prior to singulation, the externally exposed bottom surfaces of the leads are plated with copper, gold, solder, tin, nickel, palladium, or an alloy thereof to form a predetermined thickness of a plating layer. The singulation step comprises forming a burr at a peripheral side surface of the leads in the upward direction. The finished package may be marked with a recognition mark to enable a user to more easily identify the first lead.

摘要翻译： 公开了一种半导体封装及其制造方法。 平面或基本上平面的管芯焊盘设置在引线框架内，并且通过多个连接条连接到引线框架。 芯片焊盘的上表面和下表面的周边被半蚀刻以增加成品封装的透湿路径。 多个矩形引线从引线框架朝向管芯焊盘延伸，而不接触管芯焊盘。 可以在引线框架的上表面上形成镀银层。 半导体芯片安装在引线框架中的管芯焊盘的上表面上。 在消融后，将包装用硫酸（H 2 SO 4）的溶液处理，以将内部引线恢复到其原始颜色。 在分割之前，引线的外露的底表面镀有铜，金，焊料，锡，镍，钯或其合金，以形成预定厚度的镀层。 分割步骤包括在引线的周向侧表面沿向上方向形成毛刺。 完成的包装可以标记有识别标记，以使用户能够更容易地识别第一个引线。

公开(公告)号：US07102208B1

公开(公告)日：2006-09-05

申请号：US09687048

申请日：2000-10-13

申请人： Tae Heon Lee ,  Young Suk Chung ,  Mu Hwan Seo

发明人： Tae Heon Lee ,  Young Suk Chung ,  Mu Hwan Seo

IPC分类号： H01L23/495

CPC分类号： H01L21/4828 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor leadframe and a semiconductor package using same. More particularly, a semiconductor leadframe offering improved solder joint strength between a semiconductor package and a motherboard is disclosed. The leadframe comprises a plate-type frame body; a chip paddle on which a semiconductor chip may be mounted; a plurality of internal leads located radially and spaced at regular intervals about the perimeter of the chip paddle; external leads extending outward from the internal leads and with their terminals connecting to the frame body; and dam bars at the juncture of each external and internal lead for additional support and to ensure that the external leads remain exposed during subsequent encapsulation processes. The leadframe of the present invention providing additional solder joint strength through the use of internal leads having different lengths or surface areas.

摘要翻译： 半导体引线框和使用其的半导体封装。 更具体地，公开了一种提供半导体封装和母板之间的焊接强度提高的半导体引线框架。 引线框架包括板型框体; 可安装半导体芯片的芯片桨; 多个内部引线，围绕芯片桨的周边以规则的间隔径向地间隔开; 外部引线从内部引线向外延伸并且其端子连接到框架体; 并在每个外部和内部引线的接合处设有防水条，用于额外的支持，并确保外部引线在后续封装过程中保持暴露。 本发明的引线框架通过使用具有不同长度或表面积的内部引线提供额外的焊接接合强度。

公开(公告)号：US07115445B2

公开(公告)日：2006-10-03

申请号：US10763859

申请日：2004-01-23

申请人： Tae Heon Lee ,  Mu Hwan Seo

发明人： Tae Heon Lee ,  Mu Hwan Seo

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25–75% of the thickness of the leads.

摘要翻译： 公开了一种半导体封装，其包括芯片焊盘和具有多个焊盘的半导体芯片。 半导体芯片位于芯片桨的上表面上。 引线沿着芯片桨的周边间隔地形成。 引线与接合焊盘电连通。 半导体芯片，芯片焊盘和引线由封装材料封装。 本发明的半导体封装件的高度通过半刻蚀芯片片来减小芯片焊盘的厚度而使其最小化，使得芯片焊盘的厚度小于引线的厚度。 优选地，本发明的芯片桨叶是引线厚度的约25-75％。

公开(公告)号：US20080283979A1

公开(公告)日：2008-11-20

申请号：US11947505

申请日：2007-11-29

申请人： Tae Heon Lee ,  Mu Hwan Seo

发明人： Tae Heon Lee ,  Mu Hwan Seo

IPC分类号： H01L23/495 ,  H05K7/18

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.

摘要翻译： 公开了一种半导体封装，其包括芯片焊盘和具有多个焊盘的半导体芯片。 半导体芯片位于芯片桨的上表面上。 引线沿着芯片桨的周边间隔地形成。 引线与接合焊盘电连通。 半导体芯片，芯片焊盘和引线由封装材料封装。 本发明的半导体封装件的高度通过半刻蚀芯片板来减小芯片焊盘的厚度而使其最小化，使得芯片焊盘的厚度小于引线的厚度。 优选地，本发明的芯片桨叶是引线厚度的约25-75％。

公开(公告)号：US06696747B1

公开(公告)日：2004-02-24

申请号：US09687585

申请日：2000-10-13

申请人： Tae Heon Lee ,  Mu Hwan Seo

发明人： Tae Heon Lee ,  Mu Hwan Seo

IPC分类号： H01L23495

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.

摘要翻译： 公开了一种半导体封装，其包括芯片焊盘和具有多个焊盘的半导体芯片。 半导体芯片位于芯片桨的上表面上。 引线沿着芯片桨的周边间隔地形成。 引线与接合焊盘电连通。 半导体芯片，芯片焊盘和引线由封装材料封装。 本发明的半导体封装件的高度通过半刻蚀芯片片来减小芯片焊盘的厚度而使其最小化，使得芯片焊盘的厚度小于引线的厚度。 优选地，本发明的芯片桨叶是引线厚度的约25-75％。

公开(公告)号：US07321162B1

公开(公告)日：2008-01-22

申请号：US11492481

申请日：2006-07-25

申请人： Tae Heon Lee ,  Mu Hwan Seo

发明人： Tae Heon Lee ,  Mu Hwan Seo

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.

摘要翻译： 公开了一种半导体封装，其包括芯片焊盘和具有多个焊盘的半导体芯片。 半导体芯片位于芯片桨的上表面上。 引线沿着芯片桨的周边间隔地形成。 引线与接合焊盘电连通。 半导体芯片，芯片焊盘和引线由封装材料封装。 本发明的半导体封装件的高度通过半刻蚀芯片板来减小芯片焊盘的厚度而使其最小化，使得芯片焊盘的厚度小于引线的厚度。 优选地，本发明的芯片桨叶是引线厚度的约25-75％。

公开(公告)号：US06475827B1

公开(公告)日：2002-11-05

申请号：US09687532

申请日：2000-10-13

申请人： Tae Heon Lee ,  Mu Hwan Seo

发明人： Tae Heon Lee ,  Mu Hwan Seo

IPC分类号： H01L2144

CPC分类号： H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for making a packaged semiconductor having improved defect testing and increased production yield. The method includes providing a plurality of unit leadframes in a matrix, wherein each of the leadframes comprises a die pad connected to the leadframes by a plurality of tie bars, a plurality of tabs extending from each of the unit leadframes towards the respective die pad without contacting the die pad, and a plurality of dam bars provided on a boundary of the tabs. Next a semiconductor chip having a plurality of bond pads is mounted to a first surface of the die pad in each of said unit leadframes via an adhesive. The bond wires between each of the plurality of die pads are electrically connected to the respective semiconductor chip in each of the plurality of unit leadframes. Each of the unit leadframes is then encapsulated with an encapsulant. Each of the unit semiconductor packages is singulated from the matrix by cutting said dam bars between the tabs in each of the unit leadframes on two X-axes simultaneously, while leaving a connection between the tie bars and the unit leadframes intact. Then, each of the unit semiconductor packages are cut at the dam bars between the tabs on two Y-axes simultaneously, while leaving a connection between the tie bars and the unit leadframes intact. The entire matrix is next tested. Finally, the tie bars in each unit semiconductor package is cut to separate the semiconductor packages from the matrix.

摘要翻译： 一种制造具有改进的缺陷测试和提高的生产产量的封装半导体的方法。 该方法包括在矩阵中提供多个单位引线框架，其中每个引线框架包括通过多个连接条连接到引线框架的管芯焊盘，从每个单元引线框架朝向相应管芯焊盘延伸的多个突片， 接触所述管芯焊盘，以及设置在所述突出部的边界上的多个堤坝。 接下来，具有多个接合焊盘的半导体芯片通过粘合剂安装到每个所述单元引线框架中的管芯焊盘的第一表面。 多个管芯焊盘中的每一个之间的接合线电连接到多个单元引线框架中的每一个中的相应的半导体芯片。 每个单元引线框然后用密封剂封装。 每个单元半导体封装通过在两个X轴上的每个单元引线框架中的突片之间切割所述阻挡条，同时在连接条和单元引线框之间保持连接的同时，从矩阵中分离。 然后，每个单元半导体封装在两个Y轴上的突片之间的阻挡条上同时切割，同时保持连接条和单元引线框之间的连接完整。 接下来测试整个矩阵。 最后，切割每个单位半导体封装中的连接条以将半导体封装与基体分开。