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1.发明授权Pulsed-plasma system with pulsed sample bias for etching semiconductor substrates 有权具有用于蚀刻半导体衬底的脉冲样品偏置的脉冲等离子体系统公开(公告)号：US07718538B2
公开(公告)日：2010-05-18
申请号：US11677472
申请日：2007-02-21
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , C23F4/00 , H01J37/32009 , H01L21/3065 , H01L21/32137
摘要： A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
摘要翻译： 描述了具有用于蚀刻半导体结构的脉冲样本偏置的脉冲等离子体系统。 在一个实施例中，通过施加脉冲等离子体处理来去除样品的一部分，其中脉冲等离子体处理包括多个占空比。 在每个占空比的导通状态期间，向样品施加负偏压，而在每个占空比的OFF状态期间，零样本被施加到样品。 在另一个实施方案中，通过施加连续的等离子体工艺来除去样品的第一部分。 然后连续等离子体处理被终止，并且通过施加脉冲等离子体工艺来除去样品的第二部分。
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2.发明申请PULSED-PLASMA SYSTEM WITH PULSED SAMPLE BIAS FOR ETCHING SEMICONDUCTOR SUBSTRATES 有权具有用于蚀刻半导体衬底的脉冲样品偏置的脉冲等离子体系统公开(公告)号：US20080197110A1
公开(公告)日：2008-08-21
申请号：US11677472
申请日：2007-02-21
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01L21/31116 , C23F4/00 , H01J37/32009 , H01L21/3065 , H01L21/32137
摘要： A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
摘要翻译： 描述了具有用于蚀刻半导体结构的脉冲样本偏置的脉冲等离子体系统。 在一个实施例中，通过施加脉冲等离子体处理来去除样品的一部分，其中脉冲等离子体处理包括多个占空比。 在每个占空比的导通状态期间，向样品施加负偏压，而在每个占空比的OFF状态期间，零样本被施加到样品。 在另一个实施方案中，通过施加连续的等离子体工艺来除去样品的第一部分。 然后连续等离子体处理被终止，并且通过施加脉冲等离子体工艺来除去样品的第二部分。
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3.发明申请PULSED-PLASMA SYSTEM WITH PULSED REACTION GAS REPLENISH FOR ETCHING SEMICONDUCTOR STRUCTURES 有权具有脉冲反应气体的脉冲等离子体系统用于蚀刻半导体结构公开(公告)号：US20080206901A1
公开(公告)日：2008-08-28
申请号：US11678047
申请日：2007-02-22
IPC分类号： H01L21/3065
CPC分类号： H01L21/32137 , H01L21/3065 , H01L21/31116
摘要： A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.
摘要翻译： 描述了一种具有脉冲反应气体的脉冲等离子体系统，用于蚀刻半导体结构。 在一个实施例中，通过施加脉冲等离子体蚀刻工艺去除一部分样品。 脉冲等离子体蚀刻工艺包括多个占空比，其中每个占空比表示等离子体的导通状态和断开状态的组合。 等离子体由反应气体产生，其中反应气体在等离子体的关闭状态期间补充，而不是在ON状态下补充。 在另一个实施例中，通过施加连续的等离子体蚀刻工艺来移除样品的第一部分。 然后连续等离子体蚀刻工艺终止，通过施加具有脉冲反应气体补充的脉冲等离子体蚀刻工艺来除去样品的第二部分。
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公开(公告)号：US20080206900A1
公开(公告)日：2008-08-28
申请号：US11678041
申请日：2007-02-22
IPC分类号： H01L21/3065
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/31122 , H01L21/67069
摘要： A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
摘要翻译： 描述了用于蚀刻半导体结构的脉冲等离子体系统。 在一个实施例中，通过施加脉冲等离子体处理来去除样品的一部分，其中脉冲等离子体处理包括多个占空比。 占空比的导通状态具有足够短的持续时间，从而基本上抑制了与样品相邻的反应区域中的微负荷，同时占空比的关闭状态持续足够长，从而基本上能够去除一组 蚀刻来自反应区域的副产物。 在另一个实施方案中，通过施加连续的等离子体工艺来除去样品的第一部分。 然后连续等离子体处理被终止，并且通过施加脉冲等离子体工艺来除去样品的第二部分。
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公开(公告)号：US07737042B2
公开(公告)日：2010-06-15
申请号：US11678041
申请日：2007-02-22
IPC分类号： H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/31122 , H01L21/67069
摘要： A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
摘要翻译： 描述了用于蚀刻半导体结构的脉冲等离子体系统。 在一个实施例中，通过施加脉冲等离子体处理来去除样品的一部分，其中脉冲等离子体处理包括多个占空比。 占空比的导通状态具有足够短的持续时间，从而基本上抑制了与样品相邻的反应区域中的微负荷，同时占空比的关闭状态持续足够长，从而基本上能够去除一组 蚀刻来自反应区域的副产物。 在另一个实施方案中，通过施加连续的等离子体工艺来除去样品的第一部分。 然后连续等离子体处理被终止，并且通过施加脉冲等离子体工艺来除去样品的第二部分。
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6.发明授权Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductors structures 有权具有脉冲反应气体的脉冲等离子体系统补充用于蚀刻半导体结构公开(公告)号：US07771606B2
公开(公告)日：2010-08-10
申请号：US11678047
申请日：2007-02-22
CPC分类号： H01L21/32137 , H01L21/3065 , H01L21/31116
摘要： A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.
摘要翻译： 描述了一种具有脉冲反应气体的脉冲等离子体系统，用于蚀刻半导体结构。 在一个实施例中，通过施加脉冲等离子体蚀刻工艺去除一部分样品。 脉冲等离子体蚀刻工艺包括多个占空比，其中每个占空比表示等离子体的导通状态和断开状态的组合。 等离子体由反应气体产生，其中反应气体在等离子体的关闭状态期间补充，而不是在ON状态下补充。 在另一个实施例中，通过施加连续的等离子体蚀刻工艺来移除样品的第一部分。 然后连续等离子体蚀刻工艺终止，通过施加具有脉冲反应气体补充的脉冲等离子体蚀刻工艺来除去样品的第二部分。
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7.发明授权Process for etching tungsten silicide overlying polysilicon particularly in a flash memory 失效用于蚀刻覆盖多晶硅的硅化钨的工艺，特别是在闪速存储器中公开(公告)号：US07754610B2
公开(公告)日：2010-07-13
申请号：US11445709
申请日：2006-06-02
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/32136 , H01L21/28273 , H01L21/32137
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.
摘要翻译： 在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。 在过蚀刻中晶片偏置减小。 主要的蚀刻剂包括NF3和Cl2。 加入氩气以防止在密/异界面处的底切。 氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。 可以添加SiCl 4以获得额外的选择性。
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8.发明申请Process including silo-chloro passivation for etching tungsten silicide overlying polysilicon 审中-公开包括用于蚀刻硅化钨覆盖多晶硅的硅 - 氯钝化的方法公开(公告)号：US20070281479A1
公开(公告)日：2007-12-06
申请号：US11513455
申请日：2006-08-31
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/32137 , H01L29/40114
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 as an example of a silicon and chlorine containing passivating gas may be added for additional selectivity.
摘要翻译： 在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。 在过蚀刻中晶片偏置减小。 主要的蚀刻剂包括NF 3和Cl 2。 加入氩气以防止在密/异界面处的底切。 氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。 作为含硅和氯的钝化气体的实例，可以加入作为另外选择性的SiCl 4 Si 3。
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9.发明申请METHODS TO ELIMINATE "M-SHAPE" ETCH RATE PROFILE IN INDUCTIVELY COUPLED PLASMA REACTOR 有权消除电感耦合等离子体反应器中“M形”蚀刻速率曲线的方法公开(公告)号：US20080264904A1
公开(公告)日：2008-10-30
申请号：US11739428
申请日：2007-04-24
申请人： STEPHEN YUEN , Kyeong-Tae Lee , Valentin Todorow , Tae Won Kim , Anisul Khan , Shashank Deshmukh
发明人： STEPHEN YUEN , Kyeong-Tae Lee , Valentin Todorow , Tae Won Kim , Anisul Khan , Shashank Deshmukh
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01J37/321
摘要： An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.
摘要翻译： 电感耦合等离子体处理室具有带天花板的室。 第一和第二天线放置在天花板附近。 第一天线与第二天线同心。 等离子体源电源耦合到第一和第二天线。 等离子体源电源向第一天线产生第一RF功率，并向第二天线产生第二RF功率。 设置在室内的衬底支撑件。 第一天线的尺寸和衬底支撑件之间的距离使得衬底支撑件上的衬底的蚀刻速率基本上是均匀的。
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10.发明授权Methods to eliminate “M-shape” etch rate profile in inductively coupled plasma reactor 有权消除电感耦合等离子体反应器中的“M形”蚀刻速率曲线的方法公开(公告)号：US08956500B2
公开(公告)日：2015-02-17
申请号：US11739428
申请日：2007-04-24
申请人： Stephen Yuen , Kyeong-Tae Lee , Valentin Todorow , Tae Won Kim , Anisul Khan , Shashank Deshmukh
发明人： Stephen Yuen , Kyeong-Tae Lee , Valentin Todorow , Tae Won Kim , Anisul Khan , Shashank Deshmukh
IPC分类号： C23C16/00 , H01L21/306 , H01J37/32
CPC分类号： H01J37/321
摘要： An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.
摘要翻译： 电感耦合等离子体处理室具有带天花板的室。 第一和第二天线放置在天花板附近。 第一天线与第二天线同心。 等离子体源电源耦合到第一和第二天线。 等离子体源电源向第一天线产生第一RF功率，并向第二天线产生第二RF功率。 设置在室内的衬底支撑件。 第一天线的尺寸和衬底支撑件之间的距离使得衬底支撑件上的衬底的蚀刻速率基本上是均匀的。
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