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    METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20100038795A1

    公开(公告)日：2010-02-18

    申请号：US12542540

    申请日：2009-08-17

    申请人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

    发明人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

    摘要翻译： 根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开 从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割 第一种模式

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20120241834A1

    公开(公告)日：2012-09-27

    申请号：US13234052

    申请日：2011-09-15

    申请人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

    发明人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

    IPC分类号： H01L27/088 ,  H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/768 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

    摘要： According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

    摘要翻译： 根据一个实施例，半导体器件包括从元件形成区域延伸到绘图区域并且与元件形成区域中的半导体元件连接并且与绘图区域中的触点连接的互连。 基于在牺牲层的侧表面上匹配第n个（其中n是1或更大的整数）的第一侧壁膜的图案的第（n + 1）第二侧壁膜的图案形成互连。 当曝光装置的曝光波长为λ时，在元件形成区域中匹配互连的互连宽度的第一尺寸和元件形成区域中的互连间隔为（k1 / 2n）×（λ/ NA）或更小，透镜的数值孔径 的曝光装置为NA，处理参数为k1。 在绘图区域中匹配互连间隔的第二维大于第一维度。

    Method of fabricating semiconductor device and semiconductor device
    6.
    发明授权
    Method of fabricating semiconductor device and semiconductor device 有权
    制造半导体器件和半导体器件的方法

    公开(公告)号：US08183148B2

    公开(公告)日：2012-05-22

    申请号：US12542540

    申请日：2009-08-17

    申请人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

    发明人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

    摘要翻译： 根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开 从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割 第一种模式

    PATTERN DETERMINING METHOD
    9.
    发明申请
    PATTERN DETERMINING METHOD 审中-公开
    图案确定方法

    公开(公告)号：US20110047518A1

    公开(公告)日：2011-02-24

    申请号：US12860278

    申请日：2010-08-20

    申请人： Issui Aiba ,  Takafumi Taguchi ,  Hiromitsu Mashita ,  Taiga Uno ,  Fumiharu Nakajima ,  Toshiya Kotani ,  Tadahito Fujisawa

    发明人： Issui Aiba ,  Takafumi Taguchi ,  Hiromitsu Mashita ,  Taiga Uno ,  Fumiharu Nakajima ,  Toshiya Kotani ,  Tadahito Fujisawa

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36

    摘要： According to the embodiments, a first representative point is set on outline pattern data on a pattern formed in a process before a processed pattern. Then, a minimum distance from the first representative point to a peripheral pattern is calculated. Then, area of a region with no pattern, which is sandwiched by the first representative point and the peripheral pattern, in a region within a predetermined range from the first representative point is calculated. Then, it is determined whether the first representative point becomes a processing failure by using the minimum distance and the area.

    摘要翻译： 根据实施例，在处理图案之前的处理中形成的图案上的轮廓图案数据上设置第一代表点。 然后，计算从第一代表点到外围图案的最小距离。 然后，计算出与第一代表点和外围图案夹着的没有图案的区域的区域在距离第一代表点的预定范围内的区域中。 然后，通过使用最小距离和面积确定第一代表点是否变为处理失败。

    METHOD OF CORRECTING MASK PATTERN, COMPUTER PROGRAM PRODUCT, MASK PATTERN CORRECTING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF CORRECTING MASK PATTERN, COMPUTER PROGRAM PRODUCT, MASK PATTERN CORRECTING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    校正掩模图案，计算机程序产品，掩模图案校正装置的方法和制造半导体器件的方法

    公开(公告)号：US20120244707A1

    公开(公告)日：2012-09-27

    申请号：US13239019

    申请日：2011-09-21

    申请人： Taiga Uno ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Yukiyasu Arisawa

    发明人： Taiga Uno ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Yukiyasu Arisawa

    IPC分类号： G03F1/70 ,  H01L21/311 ,  G06F17/50

    CPC分类号： G03F1/36 ,  G03F1/70 ,  G03F7/70441 ,  G03F7/70941

    摘要： In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value.

    摘要翻译： 在根据实施例的校正掩模图案的方法中，对于布局中的每种类型的图案，计算用于参考闪光值的掩模图案校正量作为参考掩模校正量，以及掩模图案校正的改变量 计算与闪光值的变化量对应的量作为变化量信息。 基于从具有图案的信息提取参考掩模校正量和变化量信息相关联的参考掩模校正量和对应于图案的改变量信息，创建与图案的闪光值相对应的掩模图案 并且基于图案的耀斑值和参考闪光值之间的差异。