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    Threshold voltage tuning for fin-based integrated circuit device
    1.
    发明授权
    Threshold voltage tuning for fin-based integrated circuit device 有权

    公开(公告)号：US10790196B2

    公开(公告)日：2020-09-29

    申请号：US15808285

    申请日：2017-11-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/088 ,  H01L27/12

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.

    Threshold voltage tuning for fin-based integrated circuit device
    3.
    发明授权
    Threshold voltage tuning for fin-based integrated circuit device 有权

    公开(公告)号：US11322410B2

    公开(公告)日：2022-05-03

    申请号：US16199498

    申请日：2018-11-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/088 ,  H01L27/12

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

    Mechanisms for monitoring impurity in high-K dielectric film
    4.
    发明授权
    Mechanisms for monitoring impurity in high-K dielectric film 有权
    监测高K电介质膜杂质的机理

    公开(公告)号：US09553160B2

    公开(公告)日：2017-01-24

    申请号：US14049657

    申请日：2013-10-09

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Jen Chen ,  Yen-Yu Chen ,  Chang-Sheng Lee ,  Wei Zhang

    IPC: H01L21/66 ,  G01R31/26 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28

    CPC classification number: H01L29/4966 ,  H01L21/28194 ,  H01L22/12 ,  H01L22/20 ,  H01L29/513 ,  H01L29/517

    Abstract: Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment.

    Abstract translation: 提供了在高k电介质膜中监测金属杂质的机理的实施例。 该方法包括在衬底上形成界面层。 该方法还包括在界面层上形成高k电介质膜，并且界面层和高k电介质膜在衬底上形成堆叠结构。 该方法还包括对堆叠结构进行第一厚度测量。 此外，该方法包括在第一厚度测量之后对堆叠结构进行处理，并且处理包括退火处理。 该方法还包括在处理之后对堆叠结构进行第二厚度测量。

    Semiconductor device with tunable work function
    5.
    发明授权
    Semiconductor device with tunable work function 有权
    具有可调功能的半导体器件

    公开(公告)号：US09548372B2

    公开(公告)日：2017-01-17

    申请号：US14609138

    申请日：2015-01-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Wei Zhang

    IPC: H01L29/51 ,  H01L29/423

    CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

    Abstract: The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer and a silicide layer. The substrate has a trench. The gate dielectric multi-layer overlies the trench, in which the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %. The etch stop layer is disposed on the gate dielectric multi-layer. The work function metallic layer is disposed on the etch stop layer. The barrier layer is disposed on the work function metallic layer. The silicide layer is disposed on the barrier layer.

    Abstract translation: 金属氧化物半导体结构包括衬底，栅极电介质多层，蚀刻停止层，功函数金属层，阻挡层和硅化物层。 衬底具有沟槽。 栅极电介质多层覆盖沟槽，其中栅极电介质多层包括氟浓度基本上在1at％至10at％范围内的高k覆盖层。 蚀刻停止层设置在栅极电介质多层上。 功函数金属层设置在蚀刻停止层上。 阻挡层设置在功函数金属层上。 硅化物层设置在阻挡层上。

    Threshold Voltage Tuning For Fin-Based Integrated Circuit Device
    6.
    发明申请
    Threshold Voltage Tuning For Fin-Based Integrated Circuit Device 审中-公开

    公开(公告)号：US20190139954A1

    公开(公告)日：2019-05-09

    申请号：US15808285

    申请日：2017-11-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L27/088 ,  H01L21/02 ,  H01L21/3213

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.

    Apparatus and System for Preventing Backside Peeling Defects on Semiconductor Wafers
    7.
    发明申请
    Apparatus and System for Preventing Backside Peeling Defects on Semiconductor Wafers 审中-公开
    用于防止半导体晶片背面剥离缺陷的装置和系统

    公开(公告)号：US20150000599A1

    公开(公告)日：2015-01-01

    申请号：US13929297

    申请日：2013-06-27

    Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

    Inventor： Yen-Yu Chen ,  Wei-Jen Chen ,  Yi-Chen Chiang ,  Tsang-Yang Liu ,  Chang-Sheng Lee ,  Wei-Chen Liao ,  Wei Zhang

    IPC: H01L21/02

    CPC classification number: H01L21/68742

    Abstract: A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

    Abstract translation: 一种装置包括基座和非反应性气体源。 基座具有通孔和晶片支撑表面。 每个通孔包括升降销和升降销头。 提升销在通孔中具有垂直的运动程度以提升或将基片放置在基座上。 提升销头具有至少一个流动通道结构，其从其第一表面延伸，至少部分地暴露于基座的底侧，其第二表面暴露于基座的顶侧，其中提升销。 非反应性气体源构造成通过流道结构通过基座的底侧将气体流动到晶片的背面。

    Threshold Voltage Tuning for Fin-Based Integrated Circuit Device
    9.
    发明申请
    Threshold Voltage Tuning for Fin-Based Integrated Circuit Device 有权

    公开(公告)号：US20220254687A1

    公开(公告)日：2022-08-11

    申请号：US17734327

    申请日：2022-05-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/088

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

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