公开(公告)号：US20220238636A1

公开(公告)日：2022-07-28

申请号：US17308381

申请日：2021-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Dun-Nian Yaung ,  Yu-Cheng Tsai ,  Meng-Hsien Lin ,  Ching-Chung Su ,  Jen-Cheng Liu ,  Wen-De Wang ,  Guan-Hua Chen

IPC: H01L49/02

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

公开(公告)号：US11769791B2

公开(公告)日：2023-09-26

申请号：US17308381

申请日：2021-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Dun-Nian Yaung ,  Yu-Cheng Tsai ,  Meng-Hsien Lin ,  Ching-Chung Su ,  Jen-Cheng Liu ,  Wen-De Wang ,  Guan-Hua Chen

IPC: H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L28/75 ,  H01L28/87 ,  H01L28/88 ,  H01L28/92 ,  H01L29/66181 ,  H01L29/945 ,  H01L28/40

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

公开(公告)号：US11211352B2

公开(公告)日：2021-12-28

申请号：US16589377

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bump structure overlying a bond pad. The bond pad is disposed over a semiconductor substrate. An etch stop layer overlies the bond pad. A buffer layer is disposed over the bond pad and separates the etch stop layer and the bond pad. The bump structure includes a base portion contacting an upper surface of the bond pad and an upper portion extending through the etch stop layer and the buffer layer. The base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter. The first width or diameter being greater than the second width or diameter.

公开(公告)号：US20210098405A1

公开(公告)日：2021-04-01

申请号：US16589377

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bump structure overlying a bond pad. The bond pad is disposed over a semiconductor substrate. An etch stop layer overlies the bond pad. A buffer layer is disposed over the bond pad and separates the etch stop layer and the bond pad. The bump structure includes a base portion contacting an upper surface of the bond pad and an upper portion extending through the etch stop layer and the buffer layer. The base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter. The first width or diameter being greater than the second width or diameter.

公开(公告)号：US11264368B2

公开(公告)日：2022-03-01

申请号：US16841978

申请日：2020-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L25/16 ,  H01L33/62 ,  H01L33/00

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

公开(公告)号：US09257498B1

公开(公告)日：2016-02-09

申请号：US14450532

申请日：2014-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chern-Yow Hsu ,  Shih-Chang Liu ,  Ching-Sheng Chu ,  Chia-Shiung Tsai

IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/321

CPC classification number: H01L28/60 ,  H01L21/283 ,  H01L21/321 ,  H01L21/32133 ,  H01L28/90

Abstract: Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions.

Abstract translation: 一些实施例涉及金属 - 绝缘体金属（MIM）电容器，其包括电容器底部电容（CBM）电极，布置在CBM电极上的高k电介质层和布置在电容器顶部金属（CTM）电极上的电容器顶部金属（CTM）电极） 高k电介质层。 在一些实施例中，MIM电容器包括沿着CTM电极的垂直侧壁表面延伸的CTM保护侧壁区域，并且由于金属残留物或蚀刻损伤上形成的金属残留物或蚀刻损伤而保护CTM电极免受泄漏，过早的电压击穿或烧坏 在用于形成CTM电极的一个或多个蚀刻工艺期间的侧壁。 在一些实施例中，MIM电容器包括沿着CBM电极的垂直侧壁表面延伸的CBM保护侧壁区域。 在一些实施例中，MIM电容器包括CBM和CTM保护侧壁区域。

公开(公告)号：US20160035817A1

公开(公告)日：2016-02-04

申请号：US14450532

申请日：2014-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chern-Yow Hsu ,  Shih-Chang Liu ,  Ching-Sheng Chu ,  Chia-Shiung Tsai

IPC: H01L49/02 ,  H01L21/283 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L28/60 ,  H01L21/283 ,  H01L21/321 ,  H01L21/32133 ,  H01L28/90

Abstract: Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions.

Abstract translation: 一些实施例涉及金属 - 绝缘体金属（MIM）电容器，其包括电容器底部电容（CBM）电极，布置在CBM电极上的高k电介质层和布置在电容器顶部金属（CTM）电极上的电容器顶部金属（CTM）电极） 高k电介质层。 在一些实施例中，MIM电容器包括沿着CTM电极的垂直侧壁表面延伸的CTM保护侧壁区域，并且由于金属残留物或蚀刻损伤上形成的金属残留物或蚀刻损伤而保护CTM电极免受泄漏，过早的电压击穿或烧坏 在用于形成CTM电极的一个或多个蚀刻工艺期间的侧壁。 在一些实施例中，MIM电容器包括沿着CBM电极的垂直侧壁表面延伸的CBM保护侧壁区域。 在一些实施例中，MIM电容器包括CBM和CTM保护侧壁区域。

公开(公告)号：US20210066268A1

公开(公告)日：2021-03-04

申请号：US16841978

申请日：2020-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L25/16 ,  H01L33/62 ,  H01L33/00

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

公开(公告)号：US09793339B2

公开(公告)日：2017-10-17

申请号：US14591981

申请日：2015-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L21/02 ,  H01L21/20 ,  H01L49/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/75 ,  H01L21/76224 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a MIM capacitor that includes a composite capacitor top metal (CTM) electrode and a composite capacitor bottom metal (CBM) electrode. The composite CBM electrode includes a first diffusion barrier layer overlying a first metal layer, and the composite CTM electrode includes a second diffusion barrier layer overlying a second metal layer. A dielectric layer is arranged over the composite CBM electrode, underlying the composite CTM electrode. The first and second diffusion barrier layers protect the first and second metal layers from metal that diffuses or moves from a metal line underlying the MIM capacitor to the composite CTM and CBM electrodes during manufacture. A method of manufacturing the MIM capacitor is also provided.

公开(公告)号：US20160204190A1

公开(公告)日：2016-07-14

申请号：US14591981

申请日：2015-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L49/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L28/75 ,  H01L21/76224 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a MIM capacitor that includes a composite capacitor top metal (CTM) electrode and a composite capacitor bottom metal (CBM) electrode. The composite CBM electrode includes a first diffusion barrier layer overlying a first metal layer, and the composite CTM electrode includes a second diffusion barrier layer overlying a second metal layer. A dielectric layer is arranged over the composite CBM electrode, underlying the composite CTM electrode. The first and second diffusion barrier layers protect the first and second metal layers from metal that diffuses or moves from a metal line underlying the MIM capacitor to the composite CTM and CBM electrodes during manufacture. A method of manufacturing the MIM capacitor is also provided.

Abstract translation: 本发明涉及一种包括复合电容器顶部金属（CTM）电极和复合电容器底部金属（CBM）电极的MIM电容器。 复合CBM电极包括覆盖在第一金属层上的第一扩散阻挡层，并且复合CTM电极包括覆盖在第二金属层上的第二扩散阻挡层。 电介质层布置在复合CBM电极之上，复合CTM电极下面。 第一和第二扩散阻挡层在制造期间保护第一和第二金属层免受在MIM电容器下面的金属线扩散或移动到复合CTM和CBM电极的金属。 还提供了制造MIM电容器的方法。