公开(公告)号：US20240334847A1

公开(公告)日：2024-10-03

申请号：US18738161

申请日：2024-06-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Chern-Yow Hsu

IPC分类号： H10N70/00 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8418 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76879 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

摘要： A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

公开(公告)号：US11495743B2

公开(公告)日：2022-11-08

申请号：US16866704

申请日：2020-05-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chern-Yow Hsu ,  Chung-Chiang Min ,  Shih-Chang Liu

IPC分类号： H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12

摘要： A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.

公开(公告)号：US11258007B2

公开(公告)日：2022-02-22

申请号：US17065606

申请日：2020-10-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

公开(公告)号：US20210351142A1

公开(公告)日：2021-11-11

申请号：US16866752

申请日：2020-05-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Hsuan Yeh ,  Chern-Yow Hsu

IPC分类号： H01L23/00 ,  H01L21/308

摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a bond pad layer onto a dielectric structure formed over a substrate. The dielectric structure surrounds a plurality of interconnect layers. A protective layer is formed onto the bond pad layer, and the bond pad layer and the protective layer are patterned to define a bond pad covered by the protective layer. One or more upper passivation layers are formed over the protective layer. A dry etching process is performed to form an opening extending through the one or more upper passivation layers to the protective layer. A wet etching process is performed to remove a part of the protective layer and expose an upper surface of the bond pad.

公开(公告)号：US11164836B2

公开(公告)日：2021-11-02

申请号：US16549013

申请日：2019-08-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yao-Wen Chang ,  Chern-Yow Hsu ,  Cheng-Yuan Tsai ,  Kong-Beng Thei

IPC分类号： H01L29/417 ,  H01L23/00 ,  H01L21/288 ,  H01L21/311

摘要： A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

公开(公告)号：US11158797B2

公开(公告)日：2021-10-26

申请号：US16009327

申请日：2018-06-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L45/00 ,  H01L27/24

摘要： The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

公开(公告)号：US10510952B2

公开(公告)日：2019-12-17

申请号：US15783030

申请日：2017-10-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC分类号： H01L45/00 ,  H01L43/12 ,  H01L21/311

摘要： A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch.

公开(公告)号：US20180151527A1

公开(公告)日：2018-05-31

申请号：US15711045

申请日：2017-09-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yao-Wen Chang ,  Chern-Yow Hsu ,  Cheng-Yuan Tsai ,  Kong-Beng Thei

IPC分类号： H01L23/00 ,  H01L21/311 ,  H01L21/288

CPC分类号： H01L24/13 ,  H01L21/288 ,  H01L21/31116 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02175 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10145 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13078 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13186 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029

摘要： A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

公开(公告)号：US09818935B2

公开(公告)日：2017-11-14

申请号：US15000289

申请日：2016-01-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry-Hak-Lay Chuang ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L43/04 ,  H01L27/22

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/12

摘要： Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.

公开(公告)号：US20160043306A1

公开(公告)日：2016-02-11

申请号：US14918671

申请日：2015-10-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC分类号： H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

摘要翻译： 集成电路器件包括衬底和磁隧道结（MTJ）。 MTJ至少包括钉扎层，阻挡层和自由层。 MTJ形成在衬底的表面上。 在被钉扎层，阻挡层和自由层中，自由层首先形成并且最接近表面。 这使得在蚀刻自由层之前，可以在自由层的周边区域上形成间隔物。 由蚀刻或其它自由层边界限定工艺导致的对自由层的任何损伤通过间隔物保持与隧道结一定距离。