公开(公告)号：US20230352404A1

公开(公告)日：2023-11-02

申请号：US17819678

申请日：2022-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chiang KUO ,  Guan Yu Chen ,  Hsin-Liang Chen

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/485 ,  H01L23/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/485 ,  H01L24/32 ,  H01L2224/32258

Abstract: The present disclosure describes a structure with a substrate, a circuit element, a first metallization layer, and a second metallization layer. The circuit element is formed on the substrate. The first metallization layer is disposed over the substrate and includes a first metal line electrically connected to the circuit element and first dummy metal lines extending along a first direction. The second metallization layer is disposed directly above the first metallization layer and includes a second metal line electrically connected to the first metal line and second dummy metal lines extending along a second direction. The second direction is perpendicular to the first direction.

公开(公告)号：US20240128261A1

公开(公告)日：2024-04-18

申请号：US18128129

申请日：2023-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chiang KUO ,  Yu-Hsin Fang ,  Min-Hsiung Chen

IPC: H01L27/08 ,  H01L21/3213 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L27/0805 ,  H01L21/32131 ,  H01L21/4853 ,  H01L21/56 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49838 ,  H01L28/40

Abstract: A structure and method for improving manufacturing yield of passive device dies are disclosed. The structure includes first and second groups of capacitors disposed on a substrate, an interconnect structure disposed on the first and second groups of capacitors, first and second bonding structures disposed on the first and second conductive lines, respectively, and first and second measurement structures connected to the first and second conductive lines, respectively, and configured to measure electrical properties of the first and second groups of capacitors, respectively. The interconnect structure includes first and second conductive line connected to the first and second groups of trench capacitors, respectively. The first bonding structure is electrically connected to the first group of capacitors and the second bonding structure is electrically isolated from the first and second groups of capacitors. The first and second measurement structures are electrically isolated from each other.

公开(公告)号：US20240079353A1

公开(公告)日：2024-03-07

申请号：US18128357

申请日：2023-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chiang KUO ,  Meei-Shiou Chern ,  Jyun-Ting Hou

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/642 ,  H01L21/486 ,  H01L23/5386 ,  H01L28/75 ,  H01L28/91 ,  H01L28/92 ,  H01L23/5385 ,  H01L25/0655

Abstract: A semiconductor device with capacitive structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, first and second trenches disposed in the substrate and separated from each other by a substrate region of the substrate, first, second, and third conductive layers disposed in the first and second trenches and on the substrate region in a stacked configuration, a nitride layer including first and second nitride portions disposed on the first and second trenches and on the substrate region, and first and second contact structures configured to provide first and second voltages to the first and second conductive layers. The first nitride portion is disposed on the first conductive layer and on sidewalls of the second and third conductive layers. The second nitride portion is disposed on the second conductive layer and on sidewalls of the third conductive layers.

公开(公告)号：US20220310520A1

公开(公告)日：2022-09-29

申请号：US17841526

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chiang KUO ,  Tao-Cheng LIU ,  Shih-Chi KUO ,  Tsung-Hsien LEE

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/762 ,  H01L23/532 ,  H01L21/78

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

公开(公告)号：US20210028118A1

公开(公告)日：2021-01-28

申请号：US17065979

申请日：2020-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chiang KUO ,  Tao-Cheng LIU ,  Shih-Chi KUO ,  Tsung-Hsien LEE

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/762 ,  H01L23/532 ,  H01L21/78

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

公开(公告)号：US20190035736A1

公开(公告)日：2019-01-31

申请号：US15904013

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chiang KUO ,  Tao-Cheng Liu ,  Shih-Chi Kuo ,  Tsung-Hsien Lee

IPC: H01L23/538 ,  H01L23/532 ,  H01L21/762 ,  H01L21/768

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

公开(公告)号：US20170110409A1

公开(公告)日：2017-04-20

申请号：US14883545

申请日：2015-10-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Chiang KUO ,  Ying-Hsun CHEN ,  Shih-Chi KUO ,  Tsung-Hsien LEE

IPC: H01L23/544 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L23/544 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/762 ,  H01L21/78

Abstract: A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.