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公开(公告)号:US20190293867A1
公开(公告)日:2019-09-26
申请号:US16378313
申请日:2019-04-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tao-Cheng LIU , Tsai-Hao Hung , Shih-Chi Kuo
IPC: G02B6/136 , H01L21/306 , G02B6/122 , H01L21/308
Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号:US20240302591A1
公开(公告)日:2024-09-12
申请号:US18667981
申请日:2024-05-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tao-Cheng LIU , Tsai-Hao HUNG , Shih-Chi KUO
IPC: G02B6/136 , G02B5/18 , G02B6/122 , H01L21/306 , H01L21/308
CPC classification number: G02B6/136 , G02B5/1819 , G02B5/1857 , G02B6/1225 , H01L21/30608 , H01L21/3086
Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号:US20230152521A1
公开(公告)日:2023-05-18
申请号:US18094839
申请日:2023-01-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tao-Cheng LIU , Tsai-Hao HUNG , Shih-Chi KUO
IPC: G02B6/136 , G02B6/122 , H01L21/308 , H01L21/306 , G02B5/18
CPC classification number: G02B6/136 , G02B6/1225 , H01L21/3086 , H01L21/30608 , G02B5/1819 , G02B5/1857
Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号:US20220310520A1
公开(公告)日:2022-09-29
申请号:US17841526
申请日:2022-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Fu-Chiang KUO , Tao-Cheng LIU , Shih-Chi KUO , Tsung-Hsien LEE
IPC: H01L23/538 , H01L21/768 , H01L21/762 , H01L23/532 , H01L21/78
Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
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公开(公告)号:US20210028118A1
公开(公告)日:2021-01-28
申请号:US17065979
申请日:2020-10-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Fu-Chiang KUO , Tao-Cheng LIU , Shih-Chi KUO , Tsung-Hsien LEE
IPC: H01L23/538 , H01L21/768 , H01L21/762 , H01L23/532 , H01L21/78
Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
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公开(公告)号:US20210351221A1
公开(公告)日:2021-11-11
申请号:US16867873
申请日:2020-05-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tsai-Hao HUNG , Tao-Cheng LIU , Ying-Hsun CHEN
IPC: H01L27/146
Abstract: Photonic devices and methods having an increased quantum effect length are provided. In some embodiments, a photonic device includes a substrate having a first surface. A cavity extends into the substrate from the first surface to a second surface. A semiconductor layer is disposed on the second surface in the cavity of the substrate, and a cover layer is disposed on the semiconductor layer. The semiconductor layer is configured to receive incident radiation through the substrate and to totally internally reflect the radiation at an interface between the semiconductor layer and the cover layer.
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公开(公告)号:US20210343883A1
公开(公告)日:2021-11-04
申请号:US16863989
申请日:2020-04-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tao-Cheng LIU , Tsai-Hao HUNG , Ying-Hsun CHEN
IPC: H01L31/02 , H01L31/0232 , H01L31/18
Abstract: An integrated circuit includes a photodetector. The photodetector includes a circular optical grating formed in an annular trench in a semiconductor substrate. The circular optical grating includes dielectric fins and photosensitive fins positioned in the annular trench. The circular optical grating is configured to receive incident light and to direct the incident light around the annular trench through the dielectric fins and the photosensitive fins until the light is absorbed by one of the photosensitive fins.
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公开(公告)号:US20200249397A1
公开(公告)日:2020-08-06
申请号:US16856581
申请日:2020-04-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tao-Cheng LIU , Tsai-Hao HUNG , Shih-Chi KUO
IPC: G02B6/136 , G02B6/122 , H01L21/308 , H01L21/306 , G02B5/18
Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号:US20210199889A1
公开(公告)日:2021-07-01
申请号:US17182151
申请日:2021-02-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tao-Cheng LIU , Tsai-Hao HUNG , Shih-Chi KUO
IPC: G02B6/136 , G02B6/122 , H01L21/308 , H01L21/306 , G02B5/18
Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号:US20170129767A1
公开(公告)日:2017-05-11
申请号:US15411957
申请日:2017-01-20
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
Inventor: Tsai-Hao HUNG , Shih-Chi KUO , Tsung-Hsien LEE , Tao-Cheng LIU
CPC classification number: B81B1/004 , B81B2201/0235 , B81B2201/0242 , B81B2201/0257 , B81B2203/0127 , B81B2203/0163 , B81B2203/0315 , B81B2203/04 , B81B2207/012 , B81C1/00087 , B81C1/00619 , B81C2201/0104 , B81C2201/0108 , B81C2201/0132 , B81C2203/0118
Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.
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