公开(公告)号：US20240213112A1

公开(公告)日：2024-06-27

申请号：US18169212

申请日：2023-02-15

申请人： GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Sheng-Fan YANG ,  Yen-Chao LIN ,  Chi-Ming YANG

IPC分类号： H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/3675 ,  H01L23/3185 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L24/29 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32257 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2924/0665 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/18161

摘要： A semiconductor packaging device includes a packaging module, a heat dissipation cover and a thermal interface material layer. The package module includes a substrate, and a working chip mounted on the substrate. The heat dissipation cover includes a metal cover fixed on the substrate and covering the working chip, an accommodating recess located on the metal cover to accommodate the working chip, and a plurality of protrusive columns respectively formed on the metal cover and distributed within the accommodating recess at intervals. The depth of the accommodating recess is greater than the height of each protrusive column, and the accommodating recess is greater than the working chip. The thermal interface material layer is non-solid, and located within the accommodating recess between the protrusive columns to wrap the protrusive columns and contact with the working chip, the metal cover and the protrusive columns.

公开(公告)号：US20240096763A1

公开(公告)日：2024-03-21

申请号：US18368883

申请日：2023-09-15

申请人： Littelfuse Semiconductor (Wuxi) Co., Ltd.

发明人： Lucas Zhang ,  Chao Gao ,  Lei He

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49555 ,  H01L21/4821 ,  H01L24/37 ,  H01L24/40 ,  H01L23/3121 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/32258 ,  H01L2224/37012 ,  H01L2224/37139 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/73263

摘要： A surface mounting apparatus, structure, and associated methods thereof. The surface mounting apparatus includes a housing, a lead frame, at least partially encapsulated by the housing. The lead frame includes a chip mounting surface having a chip mounting pad, and one or more first stress relief features disposed outside of the chip mounting surface. The apparatus further includes another lead frame, at least partially encapsulated by the housing. The other lead frame includes one or more second stress relief features

公开(公告)号：US20230335472A1

公开(公告)日：2023-10-19

申请号：US18028098

申请日：2021-09-23

申请人： Hitachi Energy Switzerland AG

发明人： Juergen SCHUDERER ,  Chunlei LIU ,  Slavo KICIN ,  Giovanni SALVATORE ,  Fabian MOHN

IPC分类号： H01L23/495 ,  H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49562 ,  H01L25/0657 ,  H01L23/3675 ,  H01L23/49575 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/32 ,  H01L2224/49111 ,  H01L2224/32258 ,  H01L2924/1811 ,  H01L2924/1304 ,  H01L2225/06506

摘要： The invention relates to a power semiconductor module comprising a conductive base, a conductive top, and at least two power semiconductor devices arranged between the conductive base and the conductive top. The semiconductor devices are each configured for a current of at least 1 A and/or for a voltage of at least 50 V. An insulating spacer layer is arranged on the power semiconductor devices and at least partially between the conductive base and the conductive top. At least two vertical connection elements pass from the power semiconductor devices through the spacer layer and conductively connect the conductive top with the power semiconductor devices. The spacer layer and the vertical connection elements are configured for compensating height differences of the power semiconductor devices.

公开(公告)号：US11749579B2

公开(公告)日：2023-09-05

申请号：US17188236

申请日：2021-03-01

申请人： QUALCOMM Incorporated

发明人： Aniket Patil ,  Hong Bok We ,  Bohan Yan

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/498 ,  H01L23/64

CPC分类号： H01L23/3675 ,  H01L21/4871 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/36 ,  H01L23/49568 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L23/642 ,  H01L23/645 ,  H01L23/647 ,  H01L24/83 ,  H01L2224/32258 ,  H01L2924/181

摘要： An IC package includes a heat-generating device and an electrical device on a surface of a substrate, a mold compound disposed on the electrical device, and a thermal structure disposed on the heat-generating device, without the mold compound, to improve heat dissipation. In an example, the thermal structure includes a thermal interface material (TIM) layer and a heat sink. In the example, the TIM layer extends from the heat-generating device to a height equal to or less than the mold compound and the heat sink includes a planar exterior surface above the heat-generating device and the electrical device. In an example, a first heat sink portion of the heat sink on the heat-generating device may be a different thickness than a second heat sink portion of the heat sink on the electrical device. The thermal structure reduces a thermal resistance between the heat-generating device and the heat sink.

公开(公告)号：US20180366346A1

公开(公告)日：2018-12-20

申请号：US16061251

申请日：2016-12-07

申请人： ROHM CO., LTD.

发明人： Seigo MORI ,  Masatoshi AKETA

IPC分类号： H01L21/52 ,  H01L27/04 ,  H01L29/417 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872 ,  H01L23/00

CPC分类号： H01L21/52 ,  H01L23/48 ,  H01L23/49503 ,  H01L23/49562 ,  H01L24/83 ,  H01L27/04 ,  H01L27/0694 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0619 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/417 ,  H01L29/47 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/8083 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/0603 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device according to the present invention includes a semiconductor chip having a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface, a conductive substrate onto which the semiconductor chip is die-bonded, a conductive spacer that has a planar area smaller than that of the first electrode and supports the semiconductor chip on the conductive substrate, and a resin package that seals at least the semiconductor chip and the conductive spacer.

公开(公告)号：US20180034421A1

公开(公告)日：2018-02-01

申请号：US15728303

申请日：2017-10-09

申请人： NXP USA, Inc.

发明人： David F. ABDO ,  Jeffrey K. JONES

IPC分类号： H03F1/30 ,  H03F3/193 ,  H01L23/433 ,  H01L23/48 ,  H01L23/482 ,  H01L23/36 ,  H01L23/66 ,  H01L23/00 ,  H03F1/56 ,  H03F1/02 ,  H01L21/56 ,  H03F3/195 ,  H01L23/31 ,  H01L23/522

CPC分类号： H03F1/301 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2223/6644 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/3303 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2924/1304 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1815 ,  H03F1/0288 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/447 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.

公开(公告)号：US09589938B2

公开(公告)日：2017-03-07

申请号：US14981171

申请日：2015-12-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Ying-Ju Chen

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/12 ,  H01L25/10 ,  H01L25/00 ,  H01L23/13 ,  H01L23/498 ,  H01L21/56 ,  H01L23/50

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/27 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2518 ,  H01L2224/27015 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32258 ,  H01L2224/32502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the present disclosure include devices and methods of forming the same. An embodiment is a device including a solder resist coating over a first side of a substrate, an active surface of a die bonded to the first side of the substrate by a first connector, and a surface mount device mounted to the die by a second set of connectors, the surface mount device being between the die and the first side of the substrate, the surface mount device being spaced from the solder resist coating.

摘要翻译： 本公开的实施例包括其形成装置及其方法。 一个实施例是一种器件，其包括在衬底的第一侧上的阻焊剂涂层，通过第一连接器接合到衬底的第一侧的管芯的有源表面以及通过第二组安装到管芯的表面安装器件 的表面安装器件位于管芯和衬底的第一侧之间，表面安装器件与阻焊涂层间隔开。

公开(公告)号：US09397028B2

公开(公告)日：2016-07-19

申请号：US14729234

申请日：2015-06-03

申请人： Semiconductor Components Industries, LLC

发明人： Roger M. Arbuthnot ,  Stephen St. Germain

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/492

CPC分类号： H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/67 ,  H01L24/73 ,  H01L24/83 ,  H01L24/89 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/37011 ,  H01L2224/37012 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/45015 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207 ,  H01L2224/37099

摘要： In one embodiment, methods for making semiconductor devices are disclosed.

公开(公告)号：US20150380393A1

公开(公告)日：2015-12-31

申请号：US14850339

申请日：2015-09-10

申请人： FUJI ELECTRIC CO., LTD.

发明人： Yoko NAKAMURA ,  Norihiro NASHIDA

IPC分类号： H01L25/18 ,  H05K1/18 ,  H05K3/28 ,  H01L23/00

CPC分类号： H01L25/18 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/4006 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49844 ,  H01L24/01 ,  H01L24/32 ,  H01L24/33 ,  H01L25/072 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2224/32258 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/153 ,  H01L2924/15787 ,  H01L2924/30107 ,  H05K1/0263 ,  H05K1/144 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10242 ,  H01L2924/00

摘要： A semiconductor device includes an insulating substrate including an insulating plate and a circuit plate disposed on a main surface of the insulating plate; a semiconductor chip having a front surface provided with an electrode and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate and including a metal layer; a conductive post having one end electrically and mechanically connected to the electrode and another end electrically and mechanically connected to the metal layer; a passive element fixed to the printed circuit board; and a plurality of positioning posts fixed to the printed circuit board to position the passive element.

摘要翻译： 半导体器件包括绝缘基板，绝缘基板包括绝缘板和布置在绝缘板的主表面上的电路板; 半导体芯片，具有设置有电极的前表面和固定到所述电路板的后表面; 面向绝缘基板并包括金属层的印刷电路板; 导电柱，其一端电连接和机械地连接到电极，另一端电连接和机械连接到金属层; 固定到印刷电路板的无源元件; 以及固定到印刷电路板以定位无源元件的多个定位柱。

公开(公告)号：US09099567B2

公开(公告)日：2015-08-04

申请号：US14089744

申请日：2013-11-25

申请人： Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

发明人： Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/00 ,  H05K1/14 ,  B23K20/02 ,  B23K35/02 ,  B23K20/24 ,  B23K20/16 ,  B23K20/10 ,  B23K20/00

CPC分类号： H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

摘要翻译： 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。