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公开(公告)号：US11527714B2
公开(公告)日：2022-12-13
申请号：US17339793
申请日：2021-06-04
发明人： Chun-Chieh Mo , Shih-Chi Kuo
摘要： A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.
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公开(公告)号：US11131541B2
公开(公告)日：2021-09-28
申请号：US16407799
申请日：2019-05-09
发明人： Shih-Yu Liao , Shih-Chi Kuo , Tsai-Hao Hung , Tsung-Hsien Lee
摘要： The present disclosure is directed to a method and system for monitoring a distance between a shutter and a reference point in a processing module. For example, the method includes moving a shutter relative to a substrate support in a wafer processing module and determining a distance between the shutter and a wall of the wafer processing module with a measurement device. In response to the distance being greater than a value, the method further includes transferring a substrate to the substrate support, and in response to the distance being equal to or less than the value, the method includes resetting the shutter.
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公开(公告)号：US20200259003A1
公开(公告)日：2020-08-13
申请号：US16861668
申请日：2020-04-29
发明人： Chien-Hung Lin , Chun-Chieh Mo , Shih-Chi Kuo
IPC分类号： H01L29/66 , H01L29/423 , H01L27/11573 , H01L27/1157 , H01L21/311 , H01L21/3213 , H01L29/06 , H01L29/792
摘要： A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.
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公开(公告)号：US10651237B2
公开(公告)日：2020-05-12
申请号：US16116308
申请日：2018-08-29
发明人： Chun-Chieh Mo , Shih-Chi Kuo , Tsai-Hao Hung
IPC分类号： H01L27/24 , H01L45/00 , C23C16/34 , H01L29/792 , H01L21/28 , H01L27/22 , H01L43/02 , H01L43/08 , H01L43/12 , H01L43/10
摘要： A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.
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公开(公告)号：US10508020B2
公开(公告)日：2019-12-17
申请号：US15411957
申请日：2017-01-20
发明人： Tsai-Hao Hung , Shih-Chi Kuo , Tsung-Hsien Lee , Tao-Cheng Liu
摘要： The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.
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公开(公告)号：US20190165148A1
公开(公告)日：2019-05-30
申请号：US16032601
申请日：2018-07-11
发明人： Chien-Hung Lin , Chun-Chieh Mo , Shih-Chi Kuo
IPC分类号： H01L29/66 , H01L29/792 , H01L27/1157 , H01L21/3213 , H01L21/311 , H01L29/06
摘要： A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.
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公开(公告)号：US12013570B2
公开(公告)日：2024-06-18
申请号：US18094839
申请日：2023-01-09
发明人： Tao-Cheng Liu , Tsai-Hao Hung , Shih-Chi Kuo
IPC分类号： G02B6/136 , G02B5/18 , G02B6/122 , H01L21/306 , H01L21/308
CPC分类号： G02B6/136 , G02B5/1819 , G02B5/1857 , G02B6/1225 , H01L21/30608 , H01L21/3086
摘要： A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号：US11810967B2
公开(公告)日：2023-11-07
申请号：US17865113
申请日：2022-07-14
发明人： Chien-Hung Lin , Chun-Chieh Mo , Shih-Chi Kuo
IPC分类号： H01L29/66 , H01L29/792 , H01L29/06 , H01L21/3213 , H01L21/311 , H01L29/423 , H10B43/35 , H10B43/40
CPC分类号： H01L29/66833 , H01L21/31144 , H01L21/32137 , H01L29/0649 , H01L29/42344 , H01L29/792 , H10B43/35 , H10B43/40
摘要： A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.
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公开(公告)号：US20230090628A1
公开(公告)日：2023-03-23
申请号：US17993245
申请日：2022-11-23
发明人： Chun-Chieh MO , Shih-Chi Kuo
摘要： A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.
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公开(公告)号：US11417753B2
公开(公告)日：2022-08-16
申请号：US17115831
申请日：2020-12-09
发明人： Chien-Hung Lin , Chun-Chieh Mo , Shih-Chi Kuo
IPC分类号： H01L29/66 , H01L29/792 , H01L29/06 , H01L21/3213 , H01L21/311 , H01L27/1157 , H01L27/11573 , H01L29/423
摘要： A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.
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