公开(公告)号：US20230413680A1

公开(公告)日：2023-12-21

申请号：US18228282

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Joung-Wei LIOU ,  Chin Kun LAN

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  H10B61/20 ,  H10N50/85 ,  H10N50/80 ,  H10N50/01

Abstract: The present disclosure describes an exemplary method that forms spacer stacks with metallic compound layers. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

公开(公告)号：US20140264870A1

公开(公告)日：2014-09-18

申请号：US13890320

申请日：2013-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiauhan WU ,  Joung-Wei LIOU ,  Han-Ti HSIAW

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method for forming a semiconductor device, an interconnect structure over a semiconductor substrate is provided. The interconnect structure includes a first dielectric layer and a conductive pattern inside a trench in the first dielectric layer. An etch stop layer (ESL) is formed over the interconnect structure. An interface layer comprising elemental silicon is deposited over the ESL. A second dielectric layer is then formed over the interface layer.

Abstract translation: 在形成半导体器件的方法中，提供半导体衬底上的互连结构。 互连结构包括在第一介电层中的沟槽内的第一电介质层和导电图案。 在互连结构上形成蚀刻停止层（ESL）。 包含元素硅的界面层沉积在ESL上。 然后在界面层上形成第二介电层。

公开(公告)号：US20220367380A1

公开(公告)日：2022-11-17

申请号：US17875206

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Joung-Wei LIOU ,  Greg Huang

IPC: H01L23/532 ,  H01L21/768

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to an interlayer dielectric (ILD) layer in a semiconductor device. In one example, the ILD layer is over a substrate and includes a dielectric with a dielectric constant of less than about 3.3 and a hardness of at least about 3 GPa. The semiconductor device also includes an interconnect formed in the ILD layer.

公开(公告)号：US20210119116A1

公开(公告)日：2021-04-22

申请号：US17135637

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Joung-Wei LIOU ,  Chin Kun LAN

IPC: H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: The present disclosure describes an exemplary method that forms spacer stacks with metallic compound layers. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

公开(公告)号：US20190096820A1

公开(公告)日：2019-03-28

申请号：US15940145

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Joung-Wei LIOU ,  Greg Huang

IPC: H01L23/532 ,  H01L21/768

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to an interlayer dielectric (ILD) layer in a semiconductor device. In one example, the ILD layer is over a substrate and includes a dielectric with a dielectric constant of less than about 3.3 and a hardness of at least about 3 GPa. The semiconductor device also includes an interconnect formed in the ILD layer.

公开(公告)号：US20150200133A1

公开(公告)日：2015-07-16

申请号：US14153831

申请日：2014-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHOU ,  Chung-Chi KO ,  Po-Cheng SHIH ,  Chih-Hung SUN ,  Kuang-Yuan HSU ,  Joung-Wei LIOU ,  Tze-Liang LEE

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76868 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826

Abstract: Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm.

Abstract translation: 本公开的实施例提供了一种用于形成半导体器件结构的方法。 该方法包括在半导体衬底上形成电介质层。 该方法还包括在电介质层上涂覆含碳材料。 该方法还包括用光照射介电层和含碳材料以修复电介质层，并且光具有大于约450nm的波长。