公开(公告)号：US11069419B2

公开(公告)日：2021-07-20

申请号：US16122104

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Wei Cheng Wu ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: H01L29/788 ,  G11C29/02 ,  H01L21/28 ,  G01R31/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L27/11526 ,  H01L27/11573 ,  G11C29/56 ,  H01L21/66

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.

公开(公告)号：US20170110202A1

公开(公告)日：2017-04-20

申请号：US14883791

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G11C29/02 ,  H01L23/528 ,  H01L29/51 ,  G01R31/26 ,  H01L27/115 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/544 ,  H01L29/49

CPC classification number: G01R31/2644 ,  H01L21/32133 ,  H01L21/76877 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L2223/54406 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

公开(公告)号：US10163522B2

公开(公告)日：2018-12-25

申请号：US14883787

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Wei Cheng Wu ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G02F1/1333 ,  H01L23/544 ,  G11C29/02 ,  G01R31/28 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L27/11526 ,  H01L27/11573 ,  G11C29/56 ,  H01L21/66

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.

公开(公告)号：US20190019567A1

公开(公告)日：2019-01-17

申请号：US16122104

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Wei Cheng Wu ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G11C29/02 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  G01R31/28 ,  H01L27/11568 ,  H01L29/51 ,  H01L23/544 ,  H01L29/49 ,  G11C29/56 ,  H01L21/66 ,  H01L27/11526 ,  H01L27/11573

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.

公开(公告)号：US09983257B2

公开(公告)日：2018-05-29

申请号：US14883791

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: H01L21/768 ,  G01R31/26 ,  H01L23/544 ,  H01L23/528 ,  H01L29/51 ,  H01L29/49 ,  H01L27/11568 ,  H01L29/423 ,  H01L21/3213 ,  H01L27/11573 ,  H01L21/66

CPC classification number: G01R31/2644 ,  H01L21/32133 ,  H01L21/76877 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L2223/54406 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

公开(公告)号：US20170110201A1

公开(公告)日：2017-04-20

申请号：US14883787

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Wei Cheng Wu ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G11C29/02 ,  H01L29/423 ,  H01L23/528 ,  H01L23/544 ,  G01R31/28 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/115 ,  H01L29/51

CPC classification number: G11C29/025 ,  G01R31/2884 ,  G11C2029/5602 ,  H01L21/28282 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L2223/54406 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.