公开(公告)号：US20210407963A1

公开(公告)日：2021-12-30

申请号：US16916098

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Lin ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/04 ,  H01L23/31 ,  H01L23/36 ,  H01L23/16 ,  H01L21/56

Abstract: A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.

公开(公告)号：US09661794B1

公开(公告)日：2017-05-23

申请号：US15208627

申请日：2016-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shou-Zen Chang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Kai-Chiang Wu ,  Wei-Ting Lin

IPC: H05K13/02 ,  H01L23/538 ,  H01L23/00 ,  H05K3/34 ,  H05K13/04 ,  H01L21/683

CPC classification number: H05K13/028 ,  H01L21/6835 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/73267 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H05K3/3442 ,  H05K3/3489 ,  H05K3/3494 ,  H05K13/0465

Abstract: A method of manufacturing a package structure includes at least the following steps. A wafer is provided. A flux layer is applied onto at least part of the wafer. A stencil is provided over the wafer. The stencil includes a plurality of apertures exposing the flux layer. A dispenser is provided over the stencil. A plurality of SMDs are fed over the stencil with the dispenser. The dispenser is moved to drive the SMDs into the apertures of the stencil. The stencil is removed and the flux layer is reflowed.

公开(公告)号：US11552054B2

公开(公告)日：2023-01-10

申请号：US16916098

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Lin ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/04 ,  H01L23/31 ,  H01L23/36 ,  H01L23/16 ,  H01L21/56

Abstract: A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.

公开(公告)号：US09287233B2

公开(公告)日：2016-03-15

申请号：US14093856

申请日：2013-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Liang Chen ,  Wei-Ting Lin ,  Kuan-Lin Ho ,  Yu-Chih Liu ,  Chun-Cheng Lin ,  Shih-Yen Lin

IPC: H01L23/12 ,  H01L23/34 ,  H01L23/10 ,  H01L23/00 ,  H01L23/42 ,  H01L23/367

CPC classification number: H01L24/81 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83455 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L21/563

Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.

Abstract translation: 本公开涉及具有多个不同粘合剂层的集成芯片封装，其提供用于衬底和/或IC芯片的低盖诱导应力良好翘曲控制以及相关联的形成方法。 集成芯片封装具有通过导电互连结构耦合到下面的衬底的集成芯片（IC）裸芯片。 具有第一杨氏模量的第一粘合剂层在围绕IC管芯的第一多个位置处设置在基板上。 具有不同于第一杨氏模量的第二杨氏模量的第二粘合层在围绕IC管芯的第二多个位置处设置在基板上。 盖通过第一和第二粘合剂层固定到基底上，并延伸到覆盖IC芯片的位置。

公开(公告)号：US20150155221A1

公开(公告)日：2015-06-04

申请号：US14093856

申请日：2013-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Liang Chen ,  Wei-Ting Lin ,  Kuan-Lin Ho ,  Yu-Chih Liu ,  Chun-Cheng Lin ,  Shih-Yen Lin

IPC: H01L23/433 ,  H01L23/00 ,  H01L23/16 ,  H01L23/02 ,  H01L21/52 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83455 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L21/563

Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.

Abstract translation: 本公开涉及具有多个不同粘合剂层的集成芯片封装，其提供用于衬底和/或IC芯片的低盖诱导应力良好翘曲控制以及相关联的形成方法。 集成芯片封装具有通过导电互连结构耦合到下面的衬底的集成芯片（IC）裸芯片。 具有第一杨氏模量的第一粘合剂层在围绕IC管芯的第一多个位置处设置在基板上。 具有不同于第一杨氏模量的第二杨氏模量的第二粘合层在围绕IC管芯的第二多个位置处设置在基板上。 盖通过第一和第二粘合剂层固定到基底上，并延伸到覆盖IC芯片的位置。