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公开(公告)号：US10712651B2
公开(公告)日：2020-07-14
申请号：US15906586
申请日：2018-02-27
发明人： Hung-Wen Cho , Fu-Jye Liang , Chun-Kuang Chen , Chih-Tsung Shih , Li-Jui Chen , Po-Chung Cheng , Chin-Hsiang Lin
摘要： A reticle used for collecting information for image-error compensation is provided. The reticle includes a first black border structure and a second black border structure formed over a substrate. The first and second black borders are concentric with a center of the substrate. The reticle further includes a first image structure and a second image structure formed over the substrate. The first and second image structures each has patterns representing features to be patterned on a semiconductor wafer. In a direction away from the center of the substrate, the second image structure, the second black border structure, the first image structure and the first black border structure are arranged in order.
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公开(公告)号：US10366973B2
公开(公告)日：2019-07-30
申请号：US15797842
申请日：2017-10-30
发明人： Hung-Wen Cho , Fu-Jye Liang , Chun-Kuang Chen , Chih-Tsung Shih , Li-Jui Chen , Po-Chung Cheng , Chin-Hsiang Lin
摘要： A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce a semiconductor device. The patterned layer is divided into a first portion and a second portion which is adjacent to the first portion, and a width of the second portion equals to a penumbra size of the exposure manufacturing process. The layout modification method further includes retrieving an adjusting parameter for modifying the layout of the semiconductor device; determining a compensation amount based on the adjusting parameter and the uniformity of critical dimension; and compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.
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公开(公告)号：US20230375940A1
公开(公告)日：2023-11-23
申请号：US17747939
申请日：2022-05-18
发明人： Shang-Chieh Chien , Hung-Wen Cho , Wei-Shin Cheng , Ming-Hsun Tsai , Jyun-Yan Chuang , Li-Jui Chen , Heng-Hsin Liu
IPC分类号： G03F7/20 , H01L21/027
CPC分类号： G03F7/702 , H01L21/027
摘要： A method includes: depositing a mask layer over a substrate; directing radiation reflected from a collector of a lithography system toward the mask layer according to a pattern; blocking a portion of the radiation by a blocking structure, the blocking structure being attached to a reflector of the lithography system; forming openings in the mask layer by removing regions of the mask layer exposed to the radiation; and removing material of a layer underlying the mask layer exposed by the openings.
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4.发明申请公开(公告)号：US20180144936A1
公开(公告)日：2018-05-24
申请号：US15356450
申请日：2016-11-18
发明人： Hung-Wen Cho , Wen-Chen Lu , Chaos Tsai , Feng-Jia Shiu
IPC分类号： H01L21/033 , H01L21/66 , G06F17/50 , G03F7/20 , G03F1/20
CPC分类号： H01L21/0334 , G03F1/20 , G03F1/44 , G03F7/70058 , G03F7/70625 , G03F7/70683 , G06F17/5045 , H01L22/12 , H01L22/20 , H01L22/30 , H01L23/544 , H01L2223/54426
摘要： A method includes receiving an integrated circuit (IC) layout having a pattern layer. The pattern layer includes a main layout pattern. A dimension W1 of the main layout pattern along a first direction is greater than a wafer metrology tool's critical dimension (CD) measurement upper limit. The method further includes adding a plurality of assistant layout patterns into the pattern layer. The plurality of assistant layout patterns includes a pair of CD assistant layout patterns on both sides of the main layout pattern along the first direction. The pair of CD assistant layout patterns have a substantially same dimension W2 along the first direction and are about equally distanced from the main layout pattern by a dimension D1. The dimensions W2 and D1 are greater than a printing resolution in a photolithography process and are equal to or less than the wafer metrology tool's CD measurement upper limit.
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公开(公告)号：US11150561B2
公开(公告)日：2021-10-19
申请号：US16927131
申请日：2020-07-13
发明人： Hung-Wen Cho , Fu-Jye Liang , Chun-Kuang Chen , Chih-Tsung Shih , Li-Jui Chen , Po-Chung Cheng , Chin-Hsiang Lin
摘要： A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.
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公开(公告)号：US10720419B2
公开(公告)日：2020-07-21
申请号：US16522825
申请日：2019-07-26
发明人： Hung-Wen Cho , Fu-Jye Liang , Chun-Kuang Chen , Chih-Tsung Shih , Li-Jui Chen , Po-Chung Cheng , Chin-Hsiang Lin
摘要： A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer is calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. The second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout.
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公开(公告)号：US11024623B2
公开(公告)日：2021-06-01
申请号：US16933127
申请日：2020-07-20
发明人： Hung-Wen Cho , Fu-Jye Liang , Chun-Kuang Chen , Chih-Tsung Shih , Li-Jui Chen , Po-Chung Cheng , Chin-Hsiang Lin
摘要： A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.
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8.发明授权公开(公告)号：US10276375B2
公开(公告)日：2019-04-30
申请号：US15356450
申请日：2016-11-18
发明人： Hung-Wen Cho , Wen-Chen Lu , Chaos Tsai , Feng-Jia Shiu
IPC分类号： G06F17/50 , G03F1/20 , G03F7/00 , H01L21/033 , G03F7/20 , H01L21/66 , G03F1/44 , H01L23/544
摘要： A method includes receiving an integrated circuit (IC) layout having a pattern layer. The pattern layer includes a main layout pattern. A dimension W1 of the main layout pattern along a first direction is greater than a wafer metrology tool's critical dimension (CD) measurement upper limit. The method further includes adding a plurality of assistant layout patterns into the pattern layer. The plurality of assistant layout patterns includes a pair of CD assistant layout patterns on both sides of the main layout pattern along the first direction. The pair of CD assistant layout patterns have a substantially same dimension W2 along the first direction and are about equally distanced from the main layout pattern by a dimension D1. The dimensions W2 and D1 are greater than a printing resolution in a photolithography process and are equal to or less than the wafer metrology tool's CD measurement upper limit.
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