公开(公告)号：US20180342552A1

公开(公告)日：2018-11-29

申请号：US16055298

申请日：2018-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip (IC) structure. The method may be performed by forming a first integrated chip die having one or more semiconductor devices within a first substrate, and forming a passivation layer over the first integrated chip die. The passivation layer is selectively etched to form interior sidewalls defining a first opening, and a conductive material is deposited over the passivation layer and within the first opening. The conductive material is patterned to define a conductive blocking structure that laterally extends past the one or more semiconductor devices in opposing directions. The first integrated chip die is bonded to a second integrated chip die having an array of image sensing elements within a second substrate.

公开(公告)号：US09728521B2

公开(公告)日：2017-08-08

申请号：US14806888

申请日：2015-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Cheng Tsai ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Chih-Hui Huang ,  Yan-Chih Lu ,  Ju-Shi Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L25/0657 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/80 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/215 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0104 ,  H01L2924/01072 ,  H01L2224/80

Abstract: An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.

公开(公告)号：US20170025381A1

公开(公告)日：2017-01-26

申请号：US14806888

申请日：2015-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Cheng Tsai ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Chih-Hui Huang ,  Yan-Chih Lu ,  Ju-Shi Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L25/00 ,  H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/80 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/215 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0104 ,  H01L2924/01072 ,  H01L2224/80

Abstract: An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.

Abstract translation: 提供了使用基于铜合金的混合键的集成电路（IC）。 IC包括彼此垂直堆叠的一对半导体结构。 该对半导体结构包括布置在电介质层中的对应介电层和相应的金属特征。 金属特征包括具有铜和二次金属的铜合金。 IC还包括布置在半导体结构之间的界面处的混合键。 混合键包括将电介质层结合在一起的第一键和将金属特征粘合在一起的第二键。 第二结合包括布置在金属特征的铜颗粒之间并由二次金属填充的空隙。 还提供了使用基于铜合金的混合键将一对半导体结构结合在一起的方法。

公开(公告)号：US11335716B2

公开(公告)日：2022-05-17

申请号：US16805860

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Feng-Chi Hung ,  Chen-Hsien Lin ,  Tzu-Hsuan Hsu ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

公开(公告)号：US11088192B2

公开(公告)日：2021-08-10

申请号：US16055298

申请日：2018-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip (IC) structure. The method may be performed by forming a first integrated chip die having one or more semiconductor devices within a first substrate, and forming a passivation layer over the first integrated chip die. The passivation layer is selectively etched to form interior sidewalls defining a first opening, and a conductive material is deposited over the passivation layer and within the first opening. The conductive material is patterned to define a conductive blocking structure that laterally extends past the one or more semiconductor devices in opposing directions. The first integrated chip die is bonded to a second integrated chip die having an array of image sensing elements within a second substrate.

公开(公告)号：US20210193712A1

公开(公告)日：2021-06-24

申请号：US16805860

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Feng-Chi Hung ,  Chen-Hsien Lin ,  Tzu-Hsuan Hsu ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

公开(公告)号：US10297631B2

公开(公告)日：2019-05-21

申请号：US15213519

申请日：2016-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) structure having a conductive blocking structure configured prevent radiation produced by a device within a first die from affecting an image sensing element within a second die. The IC structure has a first IC die with one or more semiconductor devices and a second IC die with an array of image sensing elements. A hybrid bonding interface region is arranged between the first and second IC die. A conductive bonding structure is arranged within the hybrid bonding interface region and is configured to electrically couple the first IC die to the second IC die. A conductive blocking structure is arranged within the hybrid bonding interface region and extends laterally between the one or more semiconductor devices and the array of image sensing elements.

公开(公告)号：US20170221950A1

公开(公告)日：2017-08-03

申请号：US15213519

申请日：2016-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/05 ,  H01L2224/48451

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) structure having a conductive blocking structure configured prevent radiation produced by a device within a first die from affecting an image sensing element within a second die. The IC structure has a first IC die with one or more semiconductor devices and a second IC die with an array of image sensing elements. A hybrid bonding interface region is arranged between the first and second IC die. A conductive bonding structure is arranged within the hybrid bonding interface region and is configured to electrically couple the first IC die to the second IC die. A conductive blocking structure is arranged within the hybrid bonding interface region and extends laterally between the one or more semiconductor devices and the array of image sensing elements.