公开(公告)号：US11088192B2

公开(公告)日：2021-08-10

申请号：US16055298

申请日：2018-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip (IC) structure. The method may be performed by forming a first integrated chip die having one or more semiconductor devices within a first substrate, and forming a passivation layer over the first integrated chip die. The passivation layer is selectively etched to form interior sidewalls defining a first opening, and a conductive material is deposited over the passivation layer and within the first opening. The conductive material is patterned to define a conductive blocking structure that laterally extends past the one or more semiconductor devices in opposing directions. The first integrated chip die is bonded to a second integrated chip die having an array of image sensing elements within a second substrate.

公开(公告)号：US20170110497A1

公开(公告)日：2017-04-20

申请号：US15395071

申请日：2016-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： U-Ting Chen ,  Shu-Ting Tsai ,  Cheng-Ying Ho ,  Tzu-Hsuan Hsu ,  Shih Pei Chou

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469

Abstract: An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.

公开(公告)号：US20230317758A1

公开(公告)日：2023-10-05

申请号：US17879556

申请日：2022-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Kuan-Hua Lin ,  Keng-Yu Chou ,  Kai-Chun Hsu ,  Sung-En Lin ,  Wen-De Wang ,  Jen-Cheng Liu

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14645 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685

Abstract: An optical device with isolation structures and a method of fabricating the same are disclosed. The optical device includes a substrate having a first surface and a second surface opposite to the first surface, first and second radiation sensing devices disposed in the substrate, a first isolation structure disposed in the substrate. The first isolation structure has a first surface and a second surface opposite to the first surface. The optical device further includes a second isolation structure disposed in the substrate and on the first surface of the first isolation structure. The second isolation structure includes a metal structure and a dielectric layer surrounding the metal structure. The second isolation structure vertically extends over the first surface of the substrate.

公开(公告)号：US10297631B2

公开(公告)日：2019-05-21

申请号：US15213519

申请日：2016-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) structure having a conductive blocking structure configured prevent radiation produced by a device within a first die from affecting an image sensing element within a second die. The IC structure has a first IC die with one or more semiconductor devices and a second IC die with an array of image sensing elements. A hybrid bonding interface region is arranged between the first and second IC die. A conductive bonding structure is arranged within the hybrid bonding interface region and is configured to electrically couple the first IC die to the second IC die. A conductive blocking structure is arranged within the hybrid bonding interface region and extends laterally between the one or more semiconductor devices and the array of image sensing elements.

公开(公告)号：US20170221950A1

公开(公告)日：2017-08-03

申请号：US15213519

申请日：2016-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/05 ,  H01L2224/48451

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) structure having a conductive blocking structure configured prevent radiation produced by a device within a first die from affecting an image sensing element within a second die. The IC structure has a first IC die with one or more semiconductor devices and a second IC die with an array of image sensing elements. A hybrid bonding interface region is arranged between the first and second IC die. A conductive bonding structure is arranged within the hybrid bonding interface region and is configured to electrically couple the first IC die to the second IC die. A conductive blocking structure is arranged within the hybrid bonding interface region and extends laterally between the one or more semiconductor devices and the array of image sensing elements.

公开(公告)号：US20240170457A1

公开(公告)日：2024-05-23

申请号：US18425936

申请日：2024-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Jeng-Shyan Lin ,  Wen-I Hsu ,  Feng-Chi Hung ,  Dun-Nian Yaung ,  Ying-Ling Tsai

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7681 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/04 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/83 ,  H01L24/91 ,  H01L25/50 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/24147 ,  H01L2224/32146 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2224/73227 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014

Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

公开(公告)号：US20180342552A1

公开(公告)日：2018-11-29

申请号：US16055298

申请日：2018-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip (IC) structure. The method may be performed by forming a first integrated chip die having one or more semiconductor devices within a first substrate, and forming a passivation layer over the first integrated chip die. The passivation layer is selectively etched to form interior sidewalls defining a first opening, and a conductive material is deposited over the passivation layer and within the first opening. The conductive material is patterned to define a conductive blocking structure that laterally extends past the one or more semiconductor devices in opposing directions. The first integrated chip die is bonded to a second integrated chip die having an array of image sensing elements within a second substrate.