公开(公告)号：US20240274691A1

公开(公告)日：2024-08-15

申请号：US18651757

申请日：2024-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Kuo-Hui Chang ,  Yi-Cheng Chao

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/4966

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

公开(公告)号：US20220359726A1

公开(公告)日：2022-11-10

申请号：US17872562

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Kuo-Hui Chang ,  Yi-Cheng Chao

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

公开(公告)号：US10411113B2

公开(公告)日：2019-09-10

申请号：US14818965

申请日：2015-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Kuo-Hui Chang ,  Yi-Cheng Chao

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

公开(公告)号：US09818841B2

公开(公告)日：2017-11-14

申请号：US14713517

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chai-Wei Chang ,  Che-Cheng Chang ,  Po-Chi Wu ,  Yi-Cheng Chao

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/76 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/3081 ,  H01L29/42356 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. In addition, the gate structure includes a gate dielectric layer formed over the substrate and a work function metal layer formed over the gate dielectric layer. The gate structure further includes a gate electrode layer formed over the work function metal layer. In addition, a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer.

公开(公告)号：US09818648B2

公开(公告)日：2017-11-14

申请号：US15236765

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Yi-Cheng Chao ,  Chai-Wei Chang ,  Po-Chi Wu ,  Jung-Jui Li

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/6681

Abstract: Methods for forming the fin field effect transistor (FinFET) device structure are provided. The method includes forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, and a number of the first fin structures is greater than a number of the second fin structures. The method also includes forming a sacrificial layer on the first fin structures and the second fin structures and performing an etching process to the sacrificial layer to form an isolation structure on the substrate.

公开(公告)号：US20210013338A1

公开(公告)日：2021-01-14

申请号：US17034176

申请日：2020-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Jung-Jui Li ,  Ya-Lan Chang ,  Yi-Cheng Chao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

公开(公告)号：US10312149B1

公开(公告)日：2019-06-04

申请号：US15810831

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Yi-Cheng Chao ,  Chai-Wei Chang ,  Po-Chi Wu ,  Jung-Jui Li

IPC: H01L21/8234 ,  H01L29/66

Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET structure includes a substrate, and the substrate includes a first region and a second region. The FinFET structure includes a first plurality of fin structures formed on the first region and a second plurality of fin structures formed on the second region. A density of the first plurality of fin structures is greater than a density of the second plurality of fin structures. The FinFET structure also includes a plurality of protruding structures between two adjacent second plurality of fin structures in the second region and an isolation structure formed on the substrate. The isolation structure has a gap height between the first plurality of fin structures and the second plurality of fin structures.

公开(公告)号：US20230119022A1

公开(公告)日：2023-04-20

申请号：US18067970

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Jung Jui Li ,  Ya-Lan Chang ,  Yi-Cheng Chao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

公开(公告)号：US11532748B2

公开(公告)日：2022-12-20

申请号：US17034176

申请日：2020-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Jung-Jui Li ,  Ya-Lan Chang ,  Yi-Cheng Chao

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

公开(公告)号：US10090396B2

公开(公告)日：2018-10-02

申请号：US14831409

申请日：2015-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Jung-Jui Li ,  Ya-Lan Chang ,  Yi-Cheng Chao

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/02

Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.