公开(公告)号：US10347741B1

公开(公告)日：2019-07-09

申请号：US15991270

申请日：2018-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Ju Liang ,  De-Wei Yu ,  Yi-Cheng Li ,  Chien-Hao Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/31 ,  H01L21/3105 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02

Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes reflowing the conformal film. The method includes forming a cap layer on the reflowed film. The method includes depositing a crystalline film on the cap layer. The method includes crystallizing the reflowed film and the cap layer after depositing the crystalline film.

公开(公告)号：US11677015B2

公开(公告)日：2023-06-13

申请号：US17109895

申请日：2020-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen Chiu ,  Yi Che Chan ,  Lun-Kuang Tan ,  Zheng-Yang Pan ,  Cheng-Po Chau ,  Pin-Ju Liang ,  Hung-Yao Chen ,  De-Wei Yu ,  Yi-Cheng Li

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/66818 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/6681 ,  H01L29/7851

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

公开(公告)号：US20210375688A1

公开(公告)日：2021-12-02

申请号：US16888515

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Wen Shen ,  You-Ting Lin ,  Jiun-Ming Kuo ,  Yuan-Ching Peng ,  Yi-Cheng Li ,  Pin-Ju Liang ,  Pei-Ren Jeng

IPC: H01L21/8234 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods of rectifying a sidewall profile of a fin-shaped stack structure are provided. An example method includes forming, on a substrate, a first fin-shaped structure and a second fin-shaped structure each including a plurality of channel layers interleaved by a plurality of sacrificial layers; depositing a first silicon liner over the first fin-shaped structure and the second fin-shaped structure; depositing a dielectric layer over the substrate, the first fin-shaped structure and the second fin-shaped structure; etching back the dielectric layer to form an isolation feature between the first fin-shaped structure and the second fin-shaped structure and to remove the first silicon liner over the first fin-shaped structure and the second fin-shaped structure to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers, and epitaxially depositing a second silicon liner over the exposed sidewalls of the plurality of channel layers and the plurality of sacrificial layers.

公开(公告)号：US12191212B2

公开(公告)日：2025-01-07

申请号：US17737766

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Li ,  Pin-Ju Liang ,  Ta-Chun Ma ,  Pei-Ren Jeng ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L27/092

Abstract: A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.

公开(公告)号：US10312158B2

公开(公告)日：2019-06-04

申请号：US15670401

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Li ,  Chien-Hao Chen ,  Yung-Cheng Lu ,  Jr-Jung Lin ,  Chun-Hung Lee ,  Chao-Cheng Chen

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/108 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.

公开(公告)号：US11232988B2

公开(公告)日：2022-01-25

申请号：US16888515

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Wen Shen ,  You-Ting Lin ,  Jiun-Ming Kuo ,  Yuan-Ching Peng ,  Yi-Cheng Li ,  Pin-Ju Liang ,  Pei-Ren Jeng

IPC: H01L21/8234 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: Methods of rectifying a sidewall profile of a fin-shaped stack structure are provided. An example method includes forming, on a substrate, a first fin-shaped structure and a second fin-shaped structure each including a plurality of channel layers interleaved by a plurality of sacrificial layers; depositing a first silicon liner over the first fin-shaped structure and the second fin-shaped structure; depositing a dielectric layer over the substrate, the first fin-shaped structure and the second fin-shaped structure; etching back the dielectric layer to form an isolation feature between the first fin-shaped structure and the second fin-shaped structure and to remove the first silicon liner over the first fin-shaped structure and the second fin-shaped structure to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers, and epitaxially depositing a second silicon liner over the exposed sidewalls of the plurality of channel layers and the plurality of sacrificial layers.

公开(公告)号：US20230019633A1

公开(公告)日：2023-01-19

申请号：US17737766

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Li ,  Pin-Ju Liang ,  Ta-Chun Ma ,  Pei-Ren Jeng ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/306

Abstract: A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.

公开(公告)号：US20210366715A1

公开(公告)日：2021-11-25

申请号：US17396948

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Ma ,  Yi-Cheng Li ,  Pin-Ju Liang ,  Cheng-Po Chau ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen ,  Cheng-Hsiung Yen

IPC: H01L21/223 ,  H01L29/66 ,  H01L21/311 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.