公开(公告)号：US20240332404A1

公开(公告)日：2024-10-03

申请号：US18738771

申请日：2024-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Wei-Hao WU ,  Jia-Ni YU

IPC: H01L29/66 ,  H01L23/535 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/7851

Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

公开(公告)号：US20230253482A1

公开(公告)日：2023-08-10

申请号：US18301712

申请日：2023-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Wei-Hao WU ,  Jia-Ni YU

IPC: H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L23/535 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/0649

Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

公开(公告)号：US20230091869A1

公开(公告)日：2023-03-23

申请号：US18053021

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Ching-Wei TSAI ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kuo-Cheng CHIANG ,  Ru-Gun LIU ,  Wei-Hao WU ,  Yi-Hsiung LIN ,  Chia-Hao CHANG ,  Lei-Chun CHOU

IPC: H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20200098888A1

公开(公告)日：2020-03-26

申请号：US16142672

申请日：2018-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Wei-Hao WU ,  Jia-Ni YU

IPC: H01L29/66 ,  H01L23/535 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

公开(公告)号：US20200006085A1

公开(公告)日：2020-01-02

申请号：US16383539

申请日：2019-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen YEH ,  Yu-Tien SHEN ,  Shih-Chun HUANG ,  Po-Chin CHANG ,  Wei-Liang LIN ,  Yung-Sung YEN ,  Wei-Hao WU ,  Li-Te LIN ,  Pinyen LIN ,  Ru-Gun LIU

IPC: H01L21/3213 ,  H01L21/66

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

公开(公告)号：US20210296468A1

公开(公告)日：2021-09-23

申请号：US17339795

申请日：2021-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Wei-Hao WU ,  Jia-Ni YU

IPC: H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: A method includes forming an active fin using a hard mask as an etching mask, wherein the active fin comprises a source region, a drain region, and a channel region, the hard mask remains over the active fin after etching the semiconductive substrate, and the hard mask has a first portion vertically overlapping the source region of the active fin, a second portion vertically overlapping the channel region of the active fin, and a third portion vertically overlapping the drain region of the active fin. A sacrificial gate is formed over the second portion of the hard mask and the channel region of the active fin. The first and third portions of the hard mask are etched. After etching the first and third portions of the hard mask, a gate spacer is formed extending along sidewalls of the sacrificial gate, and the sacrificial gate is replaced with a replacement gate.

公开(公告)号：US20240332073A1

公开(公告)日：2024-10-03

申请号：US18738390

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Wei-Hao WU ,  Teng-Chun TSAI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L21/76835 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4232

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

公开(公告)号：US20200083340A1

公开(公告)日：2020-03-12

申请号：US16683486

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao WU ,  Zhi-Chang LIN ,  Ting-Hung HSU ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/08 ,  H01L27/12 ,  H01L27/06 ,  H01L21/822 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/762 ,  B82Y10/00 ,  H01L27/092 ,  H01L29/786

Abstract: A semiconductor device includes a first device formed over a substrate. The first device includes a first gate stack encircling a first nanostructure, and the first device is a logic circuit device. The semiconductor device includes a second device formed over the first device. The second device includes a second gate stack encircling a second nanostructure, and the second device is a static random access memory (SRAM).

公开(公告)号：US20150129131A1

公开(公告)日：2015-05-14

申请号：US14080616

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ching LI ,  Wei-Hao WU ,  Li-Hsiang CHAO ,  Bo-Wei WANG ,  Yen-Yu CHEN ,  Wei ZHANG

IPC: H01L21/67 ,  H01J37/32 ,  H01J37/02

CPC classification number: H01J37/32449 ,  H01J37/32357 ,  H01J37/32651 ,  H01J37/32853 ,  H01J37/32862

Abstract: A semiconductor processing apparatus includes an electromagnetic generator, an analog signal module, and an electromagnetic shield. The electromagnetic generator is capable of generating an electromagnetic field. The analog signal module is located adjacent to the electromagnetic generator and capable of generating an analog signal. The electromagnetic shield is capable of shielding the analog signal module. The electromagnetic shield includes a plurality of covering plates. Each of the covering plates and the analog signal module are apart from at least a predetermined distance.

Abstract translation: 半导体处理装置包括电磁发生器，模拟信号模块和电磁屏蔽。 电磁发生器能产生电磁场。 模拟信号模块位于电磁发生器附近，能够产生模拟信号。 电磁屏蔽能够屏蔽模拟信号模块。 电磁屏蔽包括多个覆盖板。 覆盖板和模拟信号模块中的每一个距离至少预定距离。

公开(公告)号：US20200058508A1

公开(公告)日：2020-02-20

申请号：US16210641

申请日：2018-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni YU ,  Zhi-Chang LIN ,  Wei-Hao WU ,  Huan-Chieh SU ,  Chung-Wei HSU ,  Chih-Hao WANG

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66

Abstract: A method for forming a FinFET device structure is provided. The method for foiming a FinFET device structure includes forming a fin structure and a fin isolation structure over a substrate, and forming a metal stack over the fin structure and the fin isolation structure. The method for forming a FinFET device structure also includes partially removing the metal stack so that a top surface of the fin isolation structure is exposed, and forming a dielectric material over the metal stack and covering the top surface of the fin isolation structure. The method for forming a FinFET device structure further includes patterning the dielectric material and the metal stack to form a metal gate structure and an insulating structure over the metal gate structure.