公开(公告)号：US20170365691A1

公开(公告)日：2017-12-21

申请号：US15488814

申请日：2017-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Yu Lin

IPC: H01L29/66 ,  H01L21/04 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66583 ,  H01L21/02642 ,  H01L21/0465 ,  H01L21/26586 ,  H01L21/28247 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2224/0348 ,  H01L2224/03916

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

公开(公告)号：US09627258B1

公开(公告)日：2017-04-18

申请号：US15183452

申请日：2016-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Yu Lin

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3115 ,  H01L23/522 ,  H01L27/11

CPC classification number: H01L29/66583 ,  H01L21/02642 ,  H01L21/0465 ,  H01L21/26586 ,  H01L21/28247 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2224/0348 ,  H01L2224/03916

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

公开(公告)号：US20230360992A1

公开(公告)日：2023-11-09

申请号：US18355799

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiu Chen ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L23/3171 ,  H01L25/0652 ,  H01L24/03 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/19 ,  H01L21/56 ,  H01L2224/24225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2224/03916 ,  H01L2224/1191 ,  H01L2224/73204 ,  H01L2224/05017 ,  H01L2224/13022 ,  H01L2224/16147 ,  H01L2224/13026 ,  H01L2224/16235 ,  H01L2224/211 ,  H01L2224/24145

Abstract: A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.

公开(公告)号：US20160190080A1

公开(公告)日：2016-06-30

申请号：US14957027

申请日：2015-12-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Cheih Chen ,  Sung-Huan Sun ,  Cheng-An Chang ,  Chien-Hung Wu ,  Fu-Tang Huang

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/03019 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11916 ,  H01L2224/13007 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Abstract translation: 本发明提供一种半导体结构及其制造方法。 该方法包括：提供具有导电焊盘的芯片，在导电焊盘上形成金属层，在金属层的一部分上形成钝化层，并在金属层上形成导电柱。 由于金属层被钝化层保护，因此解决了底切问题，导电柱的支撑强度增加，并且提高了产品的可靠性。

公开(公告)号：US20120299187A1

公开(公告)日：2012-11-29

申请号：US13166562

申请日：2011-06-22

Applicant: Kent Charles OERTLE ,  Wei Xia ,  Edward Law

Inventor： Kent Charles OERTLE ,  Wei Xia ,  Edward Law

IPC: H01L23/485 ,  H01L21/50

CPC classification number: H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/036 ,  H01L2224/03831 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/05552

Abstract: Embodiments of an aluminum pad thinning in bond pad for fine pitch ultra-thick aluminum pad structures are provided herein. Embodiments include a conductive structure formed on a substrate. A first passivation layer is formed over the substrate and the conductive structure, the first passivation layer having an opening formed over the conductive structure. An ultra-thick conductive structure having a thinned trench region formed over the opening of the first passivation layer. The ultra-thick conductive structure is in contact with the conductive structure. A second passivation layer formed over the first passivation region and the ultra-thick conductive structure. The second passivation layer having an opening formed over the thinned trench region of the ultra-thick conductive structure.

Abstract translation: 本文提供了用于细间距超厚铝垫结构的接合垫中的铝垫减薄的实施例。 实施例包括形成在基板上的导电结构。 第一钝化层形成在衬底和导电结构之上，第一钝化层具有形成在导电结构上的开口。 一种超厚导电结构，其具有形成在第一钝化层的开口上的减薄沟槽区。 超厚导电结构与导电结构接触。 形成在第一钝化区域和超厚导电结构上的第二钝化层。 第二钝化层具有形成在超厚导电结构的减薄的沟槽区域上的开口。

公开(公告)号：US20110049707A1

公开(公告)日：2011-03-03

申请号：US12850828

申请日：2010-08-05

Applicant: Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

Inventor： Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02311 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29011 ,  H01L2224/29022 ,  H01L2224/29034 ,  H01L2224/29076 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/0132 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: According to one embodiment, a semiconductor device includes an electrode pad, a protective layer, a bump, and a resin layer. The electrode pad is formed on a semiconductor substrate. The protective layer includes a pad opening formed in the position of the electrode pad. The bump is formed in the pad opening and electrically connected to the electrode pad. The resin layer has a space provided between the resin layer and the bump and is formed on the protective layer via a metal layer. The resin layer is formed by using an adhesive resin material.

Abstract translation: 根据一个实施例，半导体器件包括电极焊盘，保护层，凸块和树脂层。 电极焊盘形成在半导体衬底上。 保护层包括形成在电极焊盘的位置的焊盘开口。 凸块形成在焊盘开口中并电连接到电极焊盘。 树脂层具有设置在树脂层和凸块之间的空间，并通过金属层形成在保护层上。 树脂层通过使用粘合树脂材料形成。

公开(公告)号：US20230378106A1

公开(公告)日：2023-11-23

申请号：US17664113

申请日：2022-05-19

Applicant: NXP USA, Inc.

Inventor： Namrata Kanth ,  Paul Southworth ,  Scott M. Hayes ,  Dwight Lee Daniels ,  Yufu Liu ,  Jeroen Johannes Maria Zaal ,  Cheong Chiang Ng

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/16 ,  H01L24/03 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2224/81203 ,  H01L2224/03622 ,  H01L2224/0348 ,  H01L2224/03916 ,  H01L2224/0361 ,  H01L2224/05576 ,  H01L2224/05573 ,  H01L2224/05558 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05011 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2924/35121

Abstract: An electronic device substrate with a substantially planar surface formed from an electrically non-conductive material is provided with one or more metalized pads on the substantially planner surface. Each of the one or more metalized pads is surrounded by and coplanar with the first electrically nonconductive material along an outer boundary of the metalized pad. The metalized pad is patterned such that portions of the metalized pad form metalized fingers that extend radially from the outer boundary of the metalized pad in an interdigitated arrangement with the first electrically nonconductive material. The metalized pad has a solderable surface.

公开(公告)号：US11824026B2

公开(公告)日：2023-11-21

申请号：US17113480

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Sheng-Yu Wu ,  Mirng-Ji Lii ,  Chita Chuang

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/1132 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/1147 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11906 ,  H01L2224/131 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14131 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/8183 ,  H01L2224/81191 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/94 ,  H01L2224/05187 ,  H01L2924/04953 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/1144 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00012 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81805 ,  H01L2924/00014 ,  H01L2224/81825 ,  H01L2924/00014 ,  H01L2224/8183 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014

Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.

公开(公告)号：US11817361B2

公开(公告)日：2023-11-14

申请号：US17324836

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiu Chen ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L23/3171 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/03916 ,  H01L2224/05017 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/16147 ,  H01L2224/16235 ,  H01L2224/211 ,  H01L2224/24145 ,  H01L2224/24225 ,  H01L2224/73204 ,  H01L2225/0652 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548

Abstract: A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.

公开(公告)号：US20170358547A1

公开(公告)日：2017-12-14

申请号：US15687691

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Kenneth N. Hagen

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L24/13 ,  H01L22/14 ,  H01L22/20 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02215 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03914 ,  H01L2224/03916 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05565 ,  H01L2224/0557 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/05688 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/11632 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0474 ,  H01L2924/0503 ,  H01L2924/05994 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/05432

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.