公开(公告)号：US10651114B2

公开(公告)日：2020-05-12

申请号：US16224159

申请日：2018-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L27/06 ,  G11C5/06 ,  G11C7/18 ,  H01L27/10

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

公开(公告)号：US09202557B2

公开(公告)日：2015-12-01

申请号：US14033537

申请日：2013-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Wen Wang ,  Yen-Huei Chen

IPC: G11C11/00 ,  G11C11/419 ,  H01L27/11 ,  G11C8/16 ,  H01L27/06 ,  G11C5/02 ,  G11C8/08 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C8/08 ,  G11C8/16 ,  G11C11/412 ,  H01L27/0688 ,  H01L27/1104

Abstract: A semiconductor memory includes a read port array disposed on a first layer of a three-dimensional integrated circuit and a bit cell array disposed on a second layer of the three-dimensional integrated circuit. The second layer being vertically positioned above or below the first layer. At least one bit cell of the bit cell array is coupled to at least one read port cell of the read port array by a via extending from the first layer to the second layer.

Abstract translation: 半导体存储器包括设置在三维集成电路的第一层上的读取端口阵列和设置在三维集成电路的第二层上的位单元阵列。 第二层垂直定位在第一层之上或之下。 位单元阵列的至少一个位单元通过从第一层延伸到第二层的通孔耦合到读端口阵列的至少一个读端口单元。

公开(公告)号：US09997436B2

公开(公告)日：2018-06-12

申请号：US15379537

申请日：2016-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L27/10 ,  G11C5/06 ,  G11C7/18 ,  H01L27/06

CPC classification number: H01L23/481 ,  G11C5/063 ,  G11C7/18 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

公开(公告)号：US20170098596A1

公开(公告)日：2017-04-06

申请号：US15379537

申请日：2016-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  H01L27/10 ,  G11C5/06 ,  H01L25/065

CPC classification number: H01L23/481 ,  G11C5/063 ,  G11C7/18 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

公开(公告)号：US20190122960A1

公开(公告)日：2019-04-25

申请号：US16224159

申请日：2018-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  G11C7/18 ,  H01L27/06 ,  H01L27/10 ,  H01L25/065 ,  G11C5/06

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

公开(公告)号：US20180269134A1

公开(公告)日：2018-09-20

申请号：US15983786

申请日：2018-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  G11C7/18 ,  H01L27/06 ,  H01L25/065 ,  H01L27/10 ,  G11C5/06

CPC classification number: H01L23/481 ,  G11C5/063 ,  G11C7/18 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

公开(公告)号：US09524920B2

公开(公告)日：2016-12-20

申请号：US14077252

申请日：2013-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  H01L25/065 ,  G11C5/06 ,  G11C7/18 ,  H01L27/06

CPC classification number: H01L23/481 ,  G11C5/063 ,  G11C7/18 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Abstract translation: 一种三维导线的装置和方法，包括第一层中的第一存储器列段，第二层中的第二存储器列段，以及将第一存储器列段连接到第二存储器列段的导线。 在一些实施例中，导线被布置在存储器列的第一侧上的第一层中，并且位于存储器列的第二侧上的第二层中。

公开(公告)号：US10163759B2

公开(公告)日：2018-12-25

申请号：US15983786

申请日：2018-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L27/06 ,  G11C5/06 ,  G11C7/18 ,  H01L27/10

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

公开(公告)号：US20140119101A1

公开(公告)日：2014-05-01

申请号：US13665031

申请日：2012-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Li-Wen Wang ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4063 ,  G11C16/04 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1202

Abstract: Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal.

Abstract translation: 本公开的一些方面是一种方法。 在该方法中，字线电压被提供给字线，该字线耦合到多个存储器单元。 提供升压使能信号。 升压使能信号的状态表示字线上的预定位置的字线电压是否达到非零预定字线电压。 基于升压使能信号，字线电压被选择性地升压到升压的字线电压电平。

公开(公告)号：US09142275B2

公开(公告)日：2015-09-22

申请号：US13665031

申请日：2012-10-31

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Li-Wen Wang ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/00 ,  G11C8/08 ,  G11C16/04 ,  G11C8/00 ,  G11C29/02 ,  G11C11/4063 ,  G11C7/00 ,  G11C29/12

CPC classification number: G11C8/08 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4063 ,  G11C16/04 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1202

Abstract: Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal.

Abstract translation: 本公开的一些方面是一种方法。 在该方法中，字线电压被提供给字线，该字线耦合到多个存储器单元。 提供升压使能信号。 升压使能信号的状态表示字线上的预定位置的字线电压是否达到非零预定字线电压。 基于升压使能信号，字线电压被选择性地升压到升压的字线电压电平。