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    Memory cell
    2.
    发明授权
    Memory cell 有权

    公开(公告)号：US11176997B2

    公开(公告)日：2021-11-16

    申请号：US17186539

    申请日：2021-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

    IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

    Semiconductor chip having memory and logic cells
    3.
    发明授权
    Semiconductor chip having memory and logic cells 有权

    公开(公告)号：US11062739B2

    公开(公告)日：2021-07-13

    申请号：US16454076

    申请日：2019-06-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

    IPC: H01L27/11 ,  H01L27/092 ,  G11C5/06

    Abstract: A semiconductor chip is provided. The semiconductor chip includes a memory cell and a logic cell disposed aside the memory cell, and includes signal and ground lines with the memory and logic cells located therebetween. The memory cell includes first and second active structures extending along a first direction, and includes a storage transmission gate line, first through third gate lines and a read transmission gate line extending along a second direction. The storage transmission gate line includes first and second line segments, which respectively extends across the active structures. The first through third gate lines continuously extend across the first and second active structures. The read transmission gate line includes third and fourth line segments, which respectively extend across the active structures. The first through third gate lines are located between the storage and read transmission gate lines.

    WORDLINE TRACKING FOR BOOSTED-WORDLINE TIMING SCHEME
    6.
    发明申请
    WORDLINE TRACKING FOR BOOSTED-WORDLINE TIMING SCHEME 有权
    WORDLINE跟踪增强型WORDLINE时序方案

    公开(公告)号：US20140119101A1

    公开(公告)日：2014-05-01

    申请号：US13665031

    申请日：2012-10-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

    Inventor： Li-Wen Wang ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC: G11C8/08

    CPC classification number: G11C8/08 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4063 ,  G11C16/04 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1202

    Abstract: Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal.

    Abstract translation: 本公开的一些方面是一种方法。 在该方法中，字线电压被提供给字线，该字线耦合到多个存储器单元。 提供升压使能信号。 升压使能信号的状态表示字线上的预定位置的字线电压是否达到非零预定字线电压。 基于升压使能信号，字线电压被选择性地升压到升压的字线电压电平。

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