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公开(公告)号：US20240087668A1
公开(公告)日：2024-03-14
申请号：US18512792
申请日：2023-11-17
发明人： Ankita Patidar , Sandeep Kumar Goel
IPC分类号： G11C29/44 , G01R31/3183 , G01R31/3185 , G11C29/02 , G11C29/10 , G11C29/12 , G11C29/50
CPC分类号： G11C29/44 , G01R31/318342 , G01R31/318547 , G11C29/02 , G11C29/10 , G11C29/12005 , G11C29/50004 , G06F11/079
摘要： A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.
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公开(公告)号：US11879933B2
公开(公告)日：2024-01-23
申请号：US17393232
申请日：2021-08-03
发明人： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC分类号： G01R31/02 , G06F30/398 , G01R31/317 , G06F119/08 , G01R31/28
CPC分类号： G01R31/2855 , G01R31/31721 , G06F30/398 , G06F2119/08
摘要： A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, manufacturing the integrated circuit according to the integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a set of circuit blocks and a first set of heaters.
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公开(公告)号：US11837308B2
公开(公告)日：2023-12-05
申请号：US17713904
申请日：2022-04-05
发明人： Ankita Patidar , Sandeep Kumar Goel
IPC分类号： G01R31/28 , G11C29/44 , G11C29/12 , G11C29/10 , G11C29/02 , G11C29/50 , G01R31/3185 , G01R31/3183 , G06F11/07 , G01R31/3181
CPC分类号： G11C29/44 , G01R31/318342 , G01R31/318547 , G11C29/02 , G11C29/10 , G11C29/12005 , G11C29/50004 , G01R31/2837 , G01R31/31813 , G06F11/079
摘要： A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.
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公开(公告)号：US20230385498A1
公开(公告)日：2023-11-30
申请号：US18303219
申请日：2023-04-19
发明人： Sandeep Kumar Goel , Ankita Patidar
IPC分类号： G06F30/333 , G06F30/33 , G06F30/39 , G06F30/392
CPC分类号： G06F30/333 , G06F30/392 , G06F30/39 , G06F30/33
摘要： Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.
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公开(公告)号：US11663387B2
公开(公告)日：2023-05-30
申请号：US17379256
申请日：2021-07-19
发明人： Sandeep Kumar Goel , Ankita Patidar
IPC分类号： G06F30/00 , G06F30/333 , G06F30/33 , G06F30/39 , G06F30/392
CPC分类号： G06F30/333 , G06F30/33 , G06F30/39 , G06F30/392
摘要： Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.
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公开(公告)号：US11055455B1
公开(公告)日：2021-07-06
申请号：US16788949
申请日：2020-02-12
发明人： Sandeep Kumar Goel , Yun-Han Lee , Ankita Patidar
IPC分类号： G06F30/323 , G06F30/3323 , G06F30/394 , G06F30/392 , G03F1/70 , G06F119/12
摘要： A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.
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公开(公告)号：US20190094303A1
公开(公告)日：2019-03-28
申请号：US16135804
申请日：2018-09-19
发明人： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC分类号： G01R31/3185 , G01R31/317
摘要： Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
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公开(公告)号：US11727177B2
公开(公告)日：2023-08-15
申请号：US17836954
申请日：2022-06-09
发明人： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC分类号： G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F119/18 , G06F119/02
CPC分类号： G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F2119/02 , G06F2119/18
摘要： A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
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公开(公告)号：US11699010B2
公开(公告)日：2023-07-11
申请号：US17365468
申请日：2021-07-01
发明人： Sandeep Kumar Goel , Ankita Patidar , Yun-Han Lee
IPC分类号： G06F30/323 , G06F30/3323 , G06F30/392 , G06F30/394 , G03F1/70 , G06F119/12
CPC分类号： G06F30/323 , G03F1/70 , G06F30/3323 , G06F30/392 , G06F30/394 , G06F2119/12
摘要： A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.
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公开(公告)号：US11386253B2
公开(公告)日：2022-07-12
申请号：US16901641
申请日：2020-06-15
发明人： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC分类号： G06F30/333 , G01R31/3185 , G01R31/317 , G06F30/00
摘要： Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
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