公开(公告)号：US20230378140A1

公开(公告)日：2023-11-23

申请号：US18363731

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Hsien Chiang ,  Hui-Chun Chiang ,  Tzu-Sung Huang ,  Ming-Hung Tseng ,  Kris Lipu Chuang ,  Chung-Ming Weng ,  Tsung-Yuan Yu ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L25/50 ,  H01L25/105 ,  H01L24/08 ,  H01L24/02 ,  H01L2224/73204 ,  H01L2225/06586 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2224/0557 ,  H01L2224/05559 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L24/06 ,  H01L2224/06135 ,  H01L2224/0311 ,  H01L2224/0312 ,  H01L2224/02141 ,  H01L2224/08225 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L24/73

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

公开(公告)号：US20230060720A1

公开(公告)日：2023-03-02

申请号：US17460340

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Hsien Chiang ,  Hui-Chun Chiang ,  Tzu-Sung Huang ,  Ming-Hung Tseng ,  Kris Lipu Chuang ,  Chung-Ming Weng ,  Tsung-Yuan Yu ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

公开(公告)号：US12087597B2

公开(公告)日：2024-09-10

申请号：US18331961

申请日：2023-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jen-Fu Liu ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Li-Ko Yeh ,  Hui-Chun Chiang ,  Cheng-Chieh Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/2101 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2924/181 ,  H01L2924/37001

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

公开(公告)号：US20240234375A1

公开(公告)日：2024-07-11

申请号：US18429471

申请日：2024-02-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Hsien Chiang ,  Hui-Chun Chiang ,  Tzu-Sung Huang ,  Ming-Hung Tseng ,  Kris Lipu Chuang ,  Chung-Ming Weng ,  Tsung-Yuan Yu ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L25/105 ,  H01L25/50 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/02141 ,  H01L2224/0311 ,  H01L2224/0312 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/08225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

公开(公告)号：US11935871B2

公开(公告)日：2024-03-19

申请号：US17460340

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Hsien Chiang ,  Hui-Chun Chiang ,  Tzu-Sung Huang ,  Ming-Hung Tseng ,  Kris Lipu Chuang ,  Chung-Ming Weng ,  Tsung-Yuan Yu ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L25/105 ,  H01L25/50 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/02141 ,  H01L2224/0311 ,  H01L2224/0312 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/08225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

公开(公告)号：US11715646B2

公开(公告)日：2023-08-01

申请号：US17378356

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jen-Fu Liu ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Li-Ko Yeh ,  Hui-Chun Chiang ,  Cheng-Chieh Wu

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/2101 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2924/181 ,  H01L2924/37001

Abstract: A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.