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    Semiconductor Device and Method
    3.
    发明申请
    Semiconductor Device and Method 审中-公开

    公开(公告)号：US20200006533A1

    公开(公告)日：2020-01-02

    申请号：US16376293

    申请日：2019-04-05

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ji-Yin Tsai ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen ,  Yee-Chia Yeo

    IPC分类号： H01L29/66 ,  H01L29/161 ,  H01L21/223 ,  H01L29/78

    摘要： In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

    Semiconductor device having SiGe substrate, interfacial layer and high K dielectric layer
    6.
    发明授权
    Semiconductor device having SiGe substrate, interfacial layer and high K dielectric layer 有权
    具有SiGe衬底，界面层和高K电介质层的半导体器件

    公开(公告)号：US08878302B2

    公开(公告)日：2014-11-04

    申请号：US13706081

    申请日：2012-12-05

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chao-Ching Cheng ,  Ji-Yin Tsai ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

    IPC分类号： H01L21/70 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66477 ,  H01L21/28255 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an interfacial layer. An exemplary structure for a semiconductor device comprises a Si1-xGex substrate, wherein the x is greater than 0.4; a Si layer over the Si1-xGex substrate; and a gate structure disposed over the Si layer, wherein the gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion; wherein the dielectric portion comprises a layer of III-V material on the Si layer and a high-k dielectric layer adjacent to the electrode portion.

    摘要翻译： 本发明涉及集成电路制造，更具体地涉及具有界面层的半导体器件。 半导体器件的示例性结构包括Si1-xGex衬底，其中x大于0.4; Si1-xGex衬底上的Si层; 以及设置在所述Si层上的栅极结构，其中所述栅极结构包括电介质部分和设置在所述电介质部分上方的电极部分; 其中所述电介质部分包括在所述Si层上的III-V材料层和与所述电极部分相邻的高k电介质层。

    Semiconductor Devices and Methods of Manufacture Thereof
    7.
    发明申请
    Semiconductor Devices and Methods of Manufacture Thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US20140312431A1

    公开(公告)日：2014-10-23

    申请号：US14322298

    申请日：2014-07-02

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ji-Yin Tsai ,  Yao-Tsung Huang ,  Chih-Hsin Ko ,  Clement Wann

    IPC分类号： H01L27/088

    CPC分类号： H01L27/0886 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

    摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.

    摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在工件中形成沟道区域，以及在沟道区域附近形成源极或漏极区域。 源极或漏极区包括包含SiP，SiA或硅化物的接触电阻降低材料层。 源极或漏极区域还包括包含SiCP或SiCAs的沟道应力材料层。

    Semiconductor devices and methods of manufacture thereof
    9.
    发明授权
    Semiconductor devices and methods of manufacture thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US08866188B1

    公开(公告)日：2014-10-21

    申请号：US14322298

    申请日：2014-07-02

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ji-Yin Tsai ,  Yao-Tsung Huang ,  Chih-Hsin Ko ,  Clement Wann

    IPC分类号： H01L21/02 ,  H01L27/088

    CPC分类号： H01L27/0886 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

    摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.

    摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在工件中形成沟道区域，以及在沟道区域附近形成源极或漏极区域。 源极或漏极区包括包含SiP，SiA或硅化物的接触电阻降低材料层。 源极或漏极区域还包括包含SiCP或SiCAs的沟道应力材料层。

    METHOD AND MULTI-CHANNEL DEVICES WITH ANTI-PUNCH-THROUGH FEATURES
    10.
    发明公开
    METHOD AND MULTI-CHANNEL DEVICES WITH ANTI-PUNCH-THROUGH FEATURES 审中-公开

    公开(公告)号：US20230197820A1

    公开(公告)日：2023-06-22

    申请号：US17834564

    申请日：2022-06-07

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Min Jiao ,  Ji-Yin Tsai ,  Da-Wen Lin ,  Hung-Ju Chou

    IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L29/66

    CPC分类号： H01L29/42392 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/66545

    摘要： The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T1; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness t1 on the substrate at a second temperature T2; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature T3 less than T2, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor layers.