公开(公告)号：US09583393B2

公开(公告)日：2017-02-28

申请号：US15174772

申请日：2016-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Jian-An Ke ,  Tsan-Yao Chen ,  Chin-Kun Wang

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/82 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/16 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7834

Abstract: Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material.

Abstract translation: 在本公开中提供了用于外延生长一种或多种掺杂的含硅材料以形成finFET器件的源区和漏区的机理的实施例。 通过热退火将一个或多个掺杂的含硅材料中的掺杂剂驱动到相邻的轻掺杂 - 漏极（LDD）区域中以掺杂该区域。 外延生长过程使用循环沉积/沉积/蚀刻（CDDE）工艺。 在CDDE工艺的每个循环中，形成第一和第二掺杂材料，随后的蚀刻去除大部分第二掺杂材料。 第一掺杂材料具有比第二材料更高的掺杂剂浓度，并且通过第二掺杂材料防止蚀刻工艺。 CDDE工艺可以形成高度掺杂的含硅材料。

公开(公告)号：US09455200B2

公开(公告)日：2016-09-27

申请号：US14456241

申请日：2014-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Jian-An Ke

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3115

CPC classification number: H01L21/823814 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/28008 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/66818

Abstract: A method of forming a semiconductor device includes receiving a substrate with a gate structure and forming a spacer layer over the substrate and the gate structure. The method further includes implanting carbon into the spacer layer at an angle tilted away from a first direction perpendicular to a top surface of the substrate, which increases etch resistance of the spacer layer on sidewalls of the gate structure. The method optionally includes implanting germanium into the spacer layer at the first direction, which decreases etch resistance of the spacer layer overlaying the gate structure and the substrate. The method further includes etching the spacer layer to expose the gate structure, resulting in a first portion of the spacer layer on the sidewalls of the gate structure. Due to increased etch resistance, the first portion of the spacer layer maintains its profile and thickness in subsequent fabrication processes.

Abstract translation: 形成半导体器件的方法包括：接收具有栅极结构的衬底并在衬底和栅极结构上形成间隔层。 该方法还包括以垂直于衬底顶表面的第一方向倾斜的角度将碳注入到间隔层中，这增加了栅极结构侧壁上间隔层的蚀刻电阻。 该方法可选地包括在第一方向将锗注入到间隔层中，这降低了覆盖栅极结构和衬底的间隔层的抗蚀刻性。 该方法还包括蚀刻间隔层以暴露栅极结构，导致栅极结构的侧壁上的间隔层的第一部分。 由于增加的耐蚀性，间隔层的第一部分在随后的制造工艺中保持其轮廓和厚度。

公开(公告)号：US20150017776A1

公开(公告)日：2015-01-15

申请号：US14504697

申请日：2014-10-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Jian-An Ke ,  Tsan-Yao Chen ,  Chin-Kun Wang

IPC: H01L21/8234 ,  H01L21/324 ,  H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/16 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7834

Abstract: Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material.

Abstract translation: 在本公开中提供了用于外延生长一种或多种掺杂的含硅材料以形成finFET器件的源区和漏区的机理的实施例。 通过热退火将一个或多个掺杂的含硅材料中的掺杂剂驱动到相邻的轻掺杂 - 漏极（LDD）区域中以掺杂该区域。 外延生长过程使用循环沉积/沉积/蚀刻（CDDE）工艺。 在CDDE工艺的每个循环中，形成第一和第二掺杂材料，随后的蚀刻去除大部分第二掺杂材料。 第一掺杂材料具有比第二材料更高的掺杂剂浓度，并且通过第二掺杂材料防止蚀刻工艺。 CDDE工艺可以形成高度掺杂的含硅材料。

公开(公告)号：US09502298B2

公开(公告)日：2016-11-22

申请号：US14799344

申请日：2015-07-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Tsan-Yao Chen ,  Jian-An Ke

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/823418 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/02664 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described uses Cl2 as an etchant during the epitaxial formation of the S/D regions. The mechanisms involve using an asymmetric cyclic deposition and etch (ACDE) process that forms a preparation layer enable epitaxial growth of the following epitaxial layer with transistor dopants. The mechanisms also involve soaking the surface of substrate with dopant-containing precursors to enable sufficient incorporation of transistor dopants during the epitaxial growth of the S/D regions. By using Cl2 as etchants, the mechanisms also enables high throughput of the epitaxial growth of the S/D regions.

Abstract translation: 用于形成场效应晶体管（FET）的源极/漏极（S / D）区域的机构的实施例在S / D区域的外延形成期间使用Cl2作为蚀刻剂。 这些机理涉及使用不对称的循环沉积和蚀刻（ACDE）工艺，其形成制备层，从而能够利用晶体管掺杂剂对随后的外延层进行外延生长。 这些机理还涉及用含掺杂剂的前体浸泡衬底的表面，以在S / D区的外延生长期间能够充分地掺入晶体管掺杂剂。 通过使用Cl2作为蚀刻剂，这些机制还能够实现S / D区的外延生长的高通量。

公开(公告)号：US20150318212A1

公开(公告)日：2015-11-05

申请号：US14799344

申请日：2015-07-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Tsan-Yao Chen ,  Jian-An Ke

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/823418 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/02664 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described uses Cl2 as an etchant during the epitaxial formation of the S/D regions. The mechanisms involve using an asymmetric cyclic deposition and etch (ACDE) process that forms a preparation layer enable epitaxial growth of the following epitaxial layer with transistor dopants. The mechanisms also involve soaking the surface of substrate with dopant-containing precursors to enable sufficient incorporation of transistor dopants during the epitaxial growth of the S/D regions. By using Cl2 as etchants, the mechanisms also enables high throughput of the epitaxial growth of the S/D regions.

Abstract translation: 用于形成场效应晶体管（FET）的源极/漏极（S / D）区域的机构的实施例在S / D区域的外延形成期间使用Cl2作为蚀刻剂。 这些机理涉及使用不对称的循环沉积和蚀刻（ACDE）工艺，其形成制备层，从而能够利用晶体管掺杂剂对随后的外延层进行外延生长。 这些机理还涉及用含掺杂剂的前体浸泡衬底的表面，以在S / D区的外延生长期间能够充分地掺入晶体管掺杂剂。 通过使用Cl2作为蚀刻剂，这些机制还能够实现S / D区的外延生长的高通量。

公开(公告)号：US08877592B2

公开(公告)日：2014-11-04

申请号：US13829770

申请日：2013-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Jian-An Ke ,  Tsan-Yao Chen ,  Chin-Kun Wang

IPC: H01L21/336 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/16 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7834

Abstract: Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material.

Abstract translation: 在本公开中提供了用于外延生长一种或多种掺杂的含硅材料以形成finFET器件的源区和漏区的机理的实施例。 通过热退火将一个或多个掺杂的含硅材料中的掺杂剂驱动到相邻的轻掺杂 - 漏极（LDD）区域中以掺杂该区域。 外延生长过程使用循环沉积/沉积/蚀刻（CDDE）工艺。 在CDDE工艺的每个循环中，形成第一和第二掺杂材料，随后的蚀刻去除大部分第二掺杂材料。 第一掺杂材料具有比第二材料更高的掺杂剂浓度，并且通过第二掺杂材料防止蚀刻工艺。 CDDE工艺可以形成高度掺杂的含硅材料。

公开(公告)号：US10037920B2

公开(公告)日：2018-07-31

申请号：US15276475

申请日：2016-09-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Jian-An Ke

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/28008 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818

Abstract: A method of forming a semiconductor device includes receiving a substrate with a gate structure and forming a spacer layer over the substrate and the gate structure. The method further includes implanting carbon into the spacer layer at an angle tilted away from a first direction perpendicular to a top surface of the substrate, which increases etch resistance of the spacer layer on sidewalls of the gate structure. The method optionally includes implanting germanium into the spacer layer at the first direction, which decreases etch resistance of the spacer layer overlaying the gate structure and the substrate. The method further includes etching the spacer layer to expose the gate structure, resulting in a first portion of the spacer layer on the sidewalls of the gate structure. Due to increased etch resistance, the first portion of the spacer layer maintains its profile and thickness in subsequent fabrication processes.

公开(公告)号：US20160284597A1

公开(公告)日：2016-09-29

申请号：US15174772

申请日：2016-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Jian-An Ke ,  Tsan-Yao Chen ,  Chin-Kun Wang

IPC: H01L21/8234 ,  H01L21/306 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823418 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/16 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7834

Abstract: Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material.

Abstract translation: 在本公开中提供了用于外延生长一种或多种掺杂的含硅材料以形成finFET器件的源区和漏区的机理的实施例。 通过热退火将一个或多个掺杂的含硅材料中的掺杂剂驱动到相邻的轻掺杂 - 漏极（LDD）区域中以掺杂该区域。 外延生长过程使用循环沉积/沉积/蚀刻（CDDE）工艺。 在CDDE工艺的每个循环中，形成第一和第二掺杂材料，随后的蚀刻去除大部分第二掺杂材料。 第一掺杂材料具有比第二材料更高的掺杂剂浓度，并且通过第二掺杂材料防止蚀刻工艺。 CDDE工艺可以形成高度掺杂的含硅材料。

公开(公告)号：US20140273379A1

公开(公告)日：2014-09-18

申请号：US13829770

申请日：2013-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun Hsiung Tsai ,  Jian-An Ke ,  Tsan-Yao Chen ,  Chin-Kun Wang

IPC: H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/16 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7834

Abstract: Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material.

Abstract translation: 在本公开中提供了用于外延生长一种或多种掺杂的含硅材料以形成finFET器件的源区和漏区的机理的实施例。 通过热退火将一个或多个掺杂的含硅材料中的掺杂剂驱动到相邻的轻掺杂 - 漏极（LDD）区域中以掺杂该区域。 外延生长过程使用循环沉积/沉积/蚀刻（CDDE）工艺。 在CDDE工艺的每个循环中，形成第一和第二掺杂材料，随后的蚀刻去除大部分第二掺杂材料。 第一掺杂材料具有比第二材料更高的掺杂剂浓度，并且通过第二掺杂材料防止蚀刻工艺。 CDDE工艺可以形成高度掺杂的含硅材料。

公开(公告)号：US09362175B2

公开(公告)日：2016-06-07

申请号：US14504697

申请日：2014-10-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Jian-An Ke ,  Tsan-Yao Chen ,  Chin-Kun Wang

IPC: H01L21/82 ,  H01L21/20 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L29/16

CPC classification number: H01L21/823418 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/16 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7834

Abstract: Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material.

Abstract translation: 在本公开中提供了用于外延生长一种或多种掺杂的含硅材料以形成finFET器件的源区和漏区的机理的实施例。 通过热退火将一个或多个掺杂的含硅材料中的掺杂剂驱动到相邻的轻掺杂 - 漏极（LDD）区域中以掺杂该区域。 外延生长过程使用循环沉积/沉积/蚀刻（CDDE）工艺。 在CDDE工艺的每个循环中，形成第一和第二掺杂材料，随后的蚀刻去除大部分第二掺杂材料。 第一掺杂材料具有比第二材料更高的掺杂剂浓度，并且通过第二掺杂材料防止蚀刻工艺。 CDDE工艺可以形成高度掺杂的含硅材料。