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    Memory device, method of forming the same, and memory array
    4.
    发明授权
    Memory device, method of forming the same, and memory array 有权

    公开(公告)号：US11538858B2

    公开(公告)日：2022-12-27

    申请号：US17362979

    申请日：2021-06-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chien-Min Lee ,  Ming-Yuan Song ,  Yen-Lin Huang ,  Shy-Jay Lin ,  Tung-Ying Lee ,  Xinyu Bao

    IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  G11C11/18 ,  H01L43/14

    摘要： Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

    Electron-Beam Lithography Process with Multiple Columns
    7.
    发明申请
    Electron-Beam Lithography Process with Multiple Columns 有权
    具有多列的电子束光刻工艺

    公开(公告)号：US20160284504A1

    公开(公告)日：2016-09-29

    申请号：US14695617

    申请日：2015-04-24

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Wen-Chuan Wang ,  Shy-Jay Lin

    IPC分类号： H01J37/147 ,  H01J37/317

    CPC分类号： H01J37/1474 ,  H01J37/3026 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/063 ,  H01J2237/31766

    摘要： The present disclosure provides methods of electron-beam (e-beam) lithography process. The method includes loading a substrate to an electron-beam (e-beam) system such that a first subset of fields defined on the substrate is arrayed on the substrate along a first direction. The method also includes positioning a plurality of e-beam columns having a first subset of e-beam columns arrayed along the first direction. The e-beam columns of the first subset of e-beam columns are directed to different ones of the first subset of fields. The method also includes performing a first exposing process in a scan mode such that the plurality of e-beam columns scans the substrate along the first direction.

    摘要翻译： 本公开提供了电子束（电子束）光刻工艺的方法。 该方法包括将衬底加载到电子束（电子束）系统，使得限定在衬底上的场的第一子集沿着第一方向排列在衬底上。 该方法还包括定位多个电子束列，其具有沿第一方向排列的电子束列的第一子集。 电子束列的第一子集的电子束列被引导到第一子集子集中的不同子集。 该方法还包括以扫描模式执行第一曝光处理，使得多个电子束列沿第一方向扫描基板。

    Pattern generator for a lithography system
    8.
    发明授权
    Pattern generator for a lithography system 有权
    光刻系统的图案发生器

    公开(公告)号：US09291913B2

    公开(公告)日：2016-03-22

    申请号：US14679348

    申请日：2015-04-06

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chen-Hua Yu ,  Tien-I Bao ,  Chih Wei Lu ,  Jaw-Jung Shin ,  Shy-Jay Lin ,  Burn Jeng Lin

    IPC分类号： G03F7/20 ,  H01J37/00 ,  H01J37/317

    CPC分类号： G03F7/702 ,  H01J37/00 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/31789

    摘要： A pattern generator includes a mirror array plate having a mirror, at least one electrode plate disposed over the mirror array plate, a lens let disposed over the mirror, and at least one insulator layer sandwiched between the mirror array plate and the electrode plate. The electrode plate includes a first conducting layer and a second conducting layer. The lens let has a non-straight sidewall formed in the electrode plate. The pattern generator further includes at least one insulator sandwiched between two electrode plates. The non-straight sidewall can be a U-shaped sidewall or an L-shaped sidewall.

    摘要翻译： 图案发生器包括具有反射镜的反射镜阵列板，设置在反射镜阵列板上的至少一个电极板，设置在反射镜上的透镜，以及夹在反射镜阵列板和电极板之间的至少一个绝缘体层。 电极板包括第一导电层和第二导电层。 透镜让具有形成在电极板中的非直的侧壁。 图案发生器还包括夹在两个电极板之间的至少一个绝缘体。 非直的侧壁可以是U形侧壁或L形侧壁。

    Systems and methods for high-throughput and small-footprint scanning exposure for lithography
    9.
    发明授权
    Systems and methods for high-throughput and small-footprint scanning exposure for lithography 有权
    用于光刻的高通量和小尺寸扫描曝光的系统和方法

    公开(公告)号：US09229332B2

    公开(公告)日：2016-01-05

    申请号：US14030490

    申请日：2013-09-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Burn Jeng Lin ,  Shy-Jay Lin ,  Jaw-Jung Shin ,  Wen-Chuan Wang

    IPC分类号： G03B27/32 ,  G03B27/44 ,  G03B27/54 ,  H02K41/02 ,  G03F7/20

    CPC分类号： G03F7/70275 ,  G03F7/70008 ,  G03F7/7015 ,  G03F7/70208 ,  G03F7/70358 ,  G03F7/70716 ,  G03F7/70725 ,  H01L21/682

    摘要： The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.

    摘要翻译： 本公开提供了一种包括辐射源和曝光工具的光刻系统，该曝光工具包括在第一方向上密集地包装的多个曝光柱。 每个曝光列包括配置成通过辐射源的曝光区域。 该系统还包括晶片载体，其被配置为沿着垂直于第一方向的第二方向固定和移动一个或多个晶片，使得一个或多个晶片被曝光工具暴露以形成沿着第二方向的图案。 一个或多个晶片被抗蚀剂层覆盖，并且在第二方向上在晶片载体上对准。

    Method of Fabricating an Integrated Circuit with Optimized Pattern Density Uniformity
    10.
    发明申请
    Method of Fabricating an Integrated Circuit with Optimized Pattern Density Uniformity 有权
    制造具有优化图案密度均匀性的集成电路的方法

    公开(公告)号：US20150294056A1

    公开(公告)日：2015-10-15

    申请号：US14252464

    申请日：2014-04-14

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jyuh-Fuh Lin ,  Pei-Yi Liu ,  Cheng-Hung Chen ,  Wen-Chuan Wang ,  Shy-Jay Lin ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36 ,  G06F17/5009 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  Y02P90/265

    摘要： The present disclosure provides an IC method that includes receiving an IC design layout having main features; generating a plurality of space block layers to the IC design layout, each of the space block layers being associated with an isolation distance and a plurality of space blocks; calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout; calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space layers according to the main pattern density and the dummy pattern density; choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR; generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and forming a tape-out data of the modified IC design layout for IC fabrication.

    摘要翻译： 本公开提供一种IC方法，包括接收具有主要特征的IC设计布局; 向所述IC设计布局生成多个空间块层，每个所述空间块层与隔离距离和多个空间块相关联; 计算IC设计布局的主图案密度PD0和虚设图案密度PD; 根据主图案密度和虚拟图案密度计算每个空间层的IC设计布局的最小变化块虚拟密度比（LVBDDR）; 根据LVBDDR选择优化的空间块层和优化的块虚拟密度比; 根据优化的空间块层和优化的块虚拟密度比，从IC设计布局生成修改的IC设计布局; 并形成用于IC制造的改进的IC设计布局的输出数据。