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    EXTREME ULTRAVIOLET LITHOGRAPHY MASK
    1.
    发明申请
    EXTREME ULTRAVIOLET LITHOGRAPHY MASK 有权
    极致超紫外线胶片

    公开(公告)号：US20150009482A1

    公开(公告)日：2015-01-08

    申请号：US14491560

    申请日：2014-09-19

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： SHINN-SHENG YU ,  Yen-Cheng Lu ,  Anthony Yen

    IPC: G03F1/24 ,  G03F7/20

    CPC classification number: G03F1/24 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/48 ,  G03F1/58 ,  G03F7/7015 ,  G03F7/70191

    Abstract: An EUV mask includes a low thermal expansion material (LTEM) substrate, a reflective multilayer (ML) above one surface of the LTEM substrate, and a conductive layer above an opposite surface of the LTEM substrate. A capping layer is provided above the reflective ML, a buffer layer is provided above the capping layer, and an absorption stack is provided above the buffer layer. The absorption stack comprises multiple layers. A multiple patterning process is performed on the absorption stack to form multiple reflective states.

    Abstract translation: EUV掩模包括在LTEM基板的一个表面上方的低热膨胀材料（LTEM）基板，反射多层（ML）以及在LTEM基板的相对表面上方的导电层。 在反射ML上方设置覆盖层，在覆盖层上设置缓冲层，在缓冲层上设置吸收层。 吸收层包括多层。 对吸收堆叠进行多重图案化处理以形成多个反射状态。

    Extreme Ultraviolet Lithography Process and Mask with Reduced Shadow Effect and Enhanced Intensity
    2.
    发明申请
    Extreme Ultraviolet Lithography Process and Mask with Reduced Shadow Effect and Enhanced Intensity 有权
    极紫外光刻工艺和掩膜，减少阴影效应和增强强度

    公开(公告)号：US20160161839A1

    公开(公告)日：2016-06-09

    申请号：US15044003

    申请日：2016-02-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： YEN-CHENG LU ,  SHINN-SHENG YU ,  JENG-HORNG CHEN ,  ANTHONY YEN

    IPC: G03F1/24 ,  G03F1/76 ,  G03F7/20

    CPC classification number: G03F1/24 ,  G03F1/22 ,  G03F1/26 ,  G03F1/36 ,  G03F1/76 ,  G03F7/2002 ,  G03F7/2004

    Abstract: A method of forming a mask for semiconductor fabrication is disclosed. The method includes providing a substrate and forming a first reflective layer over the substrate, wherein the first reflective layer comprises pairs of alternating materials. The method further includes forming a buffer layer over the first reflective layer and forming a second reflective layer over the buffer layer. The second reflective layer has a total thickness less than 90 nanometer (nm). The method further includes patterning the second reflective layer to form a first state and a second state of the mask. A first reflection coefficient of the first state and a second reflection coefficient of the second state have a phase difference of about 180 degrees.

    Abstract translation: 公开了一种形成用于半导体制造的掩模的方法。 该方法包括提供衬底并在衬底上形成第一反射层，其中第一反射层包括成对的交替材料。 该方法还包括在第一反射层上形成缓冲层，并在缓冲层上形成第二反射层。 第二反射层的总厚度小于90纳米（nm）。 该方法还包括使第二反射层形成图案以形成掩模的第一状态和第二状态。 第一状态的第一反射系数和第二状态的第二反射系数具有约180度的相位差。

    Mask for Extreme Ultraviolet Lithography and Method of Fabricating Same
    3.
    发明申请
    Mask for Extreme Ultraviolet Lithography and Method of Fabricating Same 有权
    极紫外光刻面具及其制作方法

    公开(公告)号：US20140272686A1

    公开(公告)日：2014-09-18

    申请号：US14209780

    申请日：2014-03-13

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： YEN-CHENG LU ,  SHINN-SHENG YU ,  JENG-HORNG CHEN ,  ANTHONY YEN

    IPC: G03F1/38 ,  G03F1/64

    CPC classification number: G03F1/38 ,  G03F1/22 ,  G03F1/24

    Abstract: A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate and a patterned absorption layer disposed over the reflective multilayer. The patterned absorption layer has a mask image region and a mask border region. The exemplary mask also includes a mask border frame disposed over the mask border region. The mask border frame has a top surface and a bottom surface. The top surface is not parallel to the bottom surface.

    Abstract translation: 公开了一种掩模及其制造方法。 在一个示例中，掩模包括衬底，设置在衬底上的反射多层涂层和设置在反射多层上的图案化吸收层。 图案化吸收层具有掩模图像区域和掩模边界区域。 示例性掩模还包括设置在掩模边界区域上方的掩模边框。 面罩边框具有顶面和底面。 顶面不平行于底面。

    Extreme Ultraviolet Lithography Process and Mask
    4.
    发明申请
    Extreme Ultraviolet Lithography Process and Mask 有权
    极紫外光刻工艺和面膜

    公开(公告)号：US20160223899A1

    公开(公告)日：2016-08-04

    申请号：US15092889

    申请日：2016-04-07

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： CHIH-TSUNG SHIH ,  SHINN-SHENG YU ,  JENG-HORNG CHEN ,  ANTHONY YEN

    IPC: G03F1/24 ,  G03F7/20

    CPC classification number: G03F1/24 ,  G03F7/2004

    Abstract: A mask for extreme ultraviolet lithography (EUVL) is disclosed. The mask includes a low thermal expansion material (LTEM) layer; and a reflective multilayer (ML) above one surface of the LTEM layer, wherein the reflective ML has a first thickness in a first reflective region and a second thickness in a second reflective region, wherein the second thickness is different from the first thickness.

    Abstract translation: 公开了一种用于极紫外光刻（EUVL）的掩模。 掩模包括低热膨胀材料（LTEM）层; 以及在所述LTEM层的一个表面上方的反射多层（ML），其中所述反射ML具有在第一反射区域中的第一厚度和在第二反射区域中的第二厚度，其中所述第二厚度不同于所述第一厚度。

    Method of Fabricating an Integrated Circuit with Enhanced Defect Repairability
    5.
    发明申请
    Method of Fabricating an Integrated Circuit with Enhanced Defect Repairability 有权
    制造具有增强的缺陷可修复性的集成电路的方法

    公开(公告)号：US20150268561A1

    公开(公告)日：2015-09-24

    申请号：US14221362

    申请日：2014-03-21

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： YEN-CHENG LU ,  SHINN-SHENG YU ,  JENG-HORNG CHEN ,  ANTHONY YEN

    IPC: G03F7/20

    CPC classification number: G03F1/72 ,  G03F1/24 ,  G03F7/701 ,  G03F7/70191 ,  G03F7/7065

    Abstract: The present disclosure provides one embodiment of a method for extreme ultraviolet lithography (EUVL) process. The method includes loading a mask to a lithography system. The mask includes defect-repaired regions and defines an integrated circuit (IC) pattern thereon. The method also includes setting an illuminator of the lithography system in an illumination mode according to the IC pattern, configuring a pupil filter in the lithography system according to the illumination mode and performing a lithography exposure process to a target with the mask and the pupil filter by the lithography system in the illumination mode.

    Abstract translation: 本公开提供了一种用于极紫外光刻（EUVL）方法的实施例。 该方法包括将掩模加载到光刻系统。 掩模包括缺陷修复区域并且在其上限定集成电路（IC）图案。 该方法还包括根据IC图案在照明模式中设置光刻系统的照明器，根据照明模式在光刻系统中配置光瞳滤光器，并使用掩模和瞳孔滤光器对目标进行光刻曝光处理 通过光刻系统在照明模式下。

    Method for Integrated Circuit Patterning
    8.
    发明申请
    Method for Integrated Circuit Patterning 有权
    集成电路图案化方法

    公开(公告)号：US20150262836A1

    公开(公告)日：2015-09-17

    申请号：US14212708

    申请日：2014-03-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： YEN-CHENG LU ,  SHU-HAO CHANG ,  SHINN-SHENG YU ,  JUI-CHING WU ,  JENG-HORNG CHEN ,  ANTHONY YEN

    IPC: H01L21/311 ,  H01L21/268

    CPC classification number: G03F7/20 ,  G03F7/40 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/66795

    Abstract: Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.

    Abstract translation: 提供一种形成集成电路图案的方法。 该方法包括在衬底上形成第一层，其中第一层的蚀刻速率对诸如极紫外（EUV）辐射或电子束（e-beam）的辐射敏感。 该方法还包括在第一层上形成抗蚀剂层，并将抗蚀剂层暴露于用于图案化的辐射。 在曝光期间，响应于其中接收的辐射的能量剂量，第一层的各个部分改变其蚀刻速率。 该方法还包括显影抗蚀剂层，蚀刻第一层，以及蚀刻基板以形成图案。 第一层的辐射敏感性用于减小图案的临界尺寸变化。

    Method of Fabricating Semiconductor Integrated Circuit
    9.
    发明申请
    Method of Fabricating Semiconductor Integrated Circuit 有权
    制造半导体集成电路的方法

    公开(公告)号：US20150262815A1

    公开(公告)日：2015-09-17

    申请号：US14211483

    申请日：2014-03-14

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： CHIEH-HAN WU ,  CHUNG-JU LEE ,  TIEN-I BAO ,  TSUNG-YU CHEN ,  SHINN-SHENG YU ,  YU-FU LIN ,  JENG-HORNG CHEN

    IPC: H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308 ,  H01L21/324

    CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/2815 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431

    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first layer is deposited over a substrate. A plurality of mandrels is formed over the first layer. Guiding-spacers are formed along sidewalls of the mandrels. Then the mandrels are removed. A neutral layer (NL) and a block copolymer (BCP) layer are deposited over the first layer and the guiding-spacers. A anneal is applied to the BCP layer to form a first polymer nanostructure between the guiding-spacers and being surrounded by a second polymer nanostructure. The first polymer nanostructures locate at a same distance from the first layer. Polymer nano-blocks are formed by selectively etching the second polymer nanostructure and the NL. By using the polymer nano-blocks and the guiding spacer as etch masks, the first layer is etched to form openings. The substrate is etched through the openings to form substrate trench and substrate fin.

    Abstract translation: 公开了制造半导体集成电路（IC）的方法。 第一层沉积在衬底上。 在第一层上形成多个心轴。 引导隔离物沿心轴的侧壁形成。 然后将心轴移除。 在第一层和引导间隔物上沉积中性层（NL）和嵌段共聚物（BCP）层。 对BCP层施加退火以在引导间隔物之间​​形成第一聚合物纳米结构并被第二聚合物纳米结构包围。 第一聚合物纳米结构位于与第一层相同的距离处。 通过选择性蚀刻第二聚合物纳米结构和NL形成聚合物纳米块。 通过使用聚合物纳米块和引导间隔物作为蚀刻掩模，蚀刻第一层以形成开口。 通过开口蚀刻衬底以形成衬底沟槽和衬底鳍。

    Extreme Ultraviolet Lithography Process And Mask
    10.
    发明申请
    Extreme Ultraviolet Lithography Process And Mask 有权
    极紫外光刻工艺和面膜

    公开(公告)号：US20150227059A1

    公开(公告)日：2015-08-13

    申请号：US14692199

    申请日：2015-04-21

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： YEN-CHENG LU ,  SHINN-SHENG YU ,  JENG-HORNG CHEN ,  ANTHONY YEN

    IPC: G03F7/20

    CPC classification number: G03F7/70691 ,  G03F1/22 ,  G03F7/22 ,  G03F7/70358 ,  G03F7/70558

    Abstract: An extreme ultraviolet lithography (EUVL) process is performed on a target, such as a semiconductor wafer, having a photosensitive layer. The method includes providing a one-dimensional patterned mask along a first direction. The patterned mask includes a substrate including a first region and a second region, a multilayer mirror above the first and second regions, an absorption layer above the multilayer mirror in the second region, and a defect in the first region. The method further includes exposing the patterned mask by an illuminator and setting the patterned mask and the target in relative motion along the first direction while exposing the patterned mask. As a result, an accumulated exposure dose received by the target is an optimized exposure dose.

    Abstract translation: 对具有感光层的目标（例如半导体晶片）进行极紫外光刻（EUVL）处理。 该方法包括沿着第一方向提供一维图案化掩模。 图案化掩模包括包括第一区域和第二区域的基板，在第一和第二区域上方的多层反射镜，第二区域中的多层反射镜上方的吸收层，以及第一区域中的缺陷。 该方法还包括通过照明器曝光图案化掩模，并将图案化掩模和目标物沿着第一方向相对运动，同时暴露图案化掩模。 结果，由目标接收的累积曝光剂量是优化的曝光剂量。

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