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公开(公告)号：US09418847B2
公开(公告)日：2016-08-16
申请号：US14163287
申请日：2014-01-24
Inventor： Ching-Wei Shen , Kuan-Wen Lin , Chi-Lun Lu , Ting-Hao Hsu , Sheng-Chi Chin , Anthony Yen
IPC: G03F1/62 , H01L21/027 , G03F1/48 , G03F7/20
CPC classification number: H01L21/0274 , G03F1/48 , G03F1/62 , G03F7/70283 , G03F7/70916 , G03F7/7095
Abstract: The present disclosure provides an apparatus in semiconductor manufacturing. The apparatus includes a mask, a pellicle frame attached to the mask, and a pellicle joined to the pellicle frame thereby forming a sealed enclosure bounded by the pellicle, the pellicle frame, and the mask. The apparatus further includes photo-catalyst particles introduced into the sealed enclosure before the sealed enclosure is formed. The photo-catalyst particles prevent haze formation within the enclosure during lithography exposure processes.
Abstract translation: 本公开提供了半导体制造中的装置。 该装置包括掩模，附着于掩模的防护薄膜组件框架和接合到防护薄膜框架上的防护薄膜组件，从而形成由防护薄膜组件，防护薄膜框架和掩模限定的密封外壳。 该装置还包括在密封外壳形成之前引入到密封外壳中的光催化剂颗粒。 在光刻曝光过程中，光催化剂颗粒防止外壳内的雾化形成。
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公开(公告)号：US20140205938A1
公开(公告)日：2014-07-24
申请号：US14245642
申请日：2014-04-04
Inventor： Ching-Fang Yu , Ting-Hao Hsu , Sheng-Chi Chin
IPC: G03F1/46
Abstract: An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern.
Abstract translation: 极光紫外（EUV）掩模可以用在光刻中，例如用于制造半导体晶片的方法。 EUV掩模包括低热膨胀材料（LTEM）基板和设置在其上的反射多层（ML）。 覆盖层设置在反射ML上，并且设置在覆盖层上的图案化吸收层。 该图案包括抗反射（ARC）型图案。
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公开(公告)号：US20230366857A1
公开(公告)日：2023-11-16
申请号：US18354786
申请日：2023-07-19
Inventor： Jun-Hao Deng , Kuan-Wen Lin , Sheng-Chi Chin , Yu-Ching Lee
IPC: G01N29/44 , H01L21/288 , H01L21/02 , G01B21/16 , G01B17/00 , B08B3/04 , G01B17/02 , H01L21/66 , B08B13/00 , B08B5/02 , H01L21/67
CPC classification number: G01N29/44 , H01L21/288 , H01L21/02623 , G01B21/16 , G01B17/00 , B08B3/04 , H01L21/02041 , G01B17/025 , H01L21/02282 , H01L22/10 , B08B13/00 , B08B5/02 , G01B17/02 , H01L21/67253 , G01N2291/044
Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
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公开(公告)号：US10859908B2
公开(公告)日：2020-12-08
申请号：US15829814
申请日：2017-12-01
Inventor： Chun-Hao Tseng , Sheng-Chi Chin , Yuan-Chih Chu
Abstract: A method for fabricating a pellicle assembly for a lithography process includes providing a carrier. A membrane layer is fabricated over the carrier. A pellicle frame is attached to the membrane layer. The carrier is then separated from the membrane layer using a release treatment process.
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公开(公告)号：US20190072849A1
公开(公告)日：2019-03-07
申请号：US16181637
申请日：2018-11-06
Inventor： Yu-Ching Lee , Ching-Fang Yu , Chun-Hung Lin , Ting-Hao Hsu , Ching-Hsiang Chang , Sheng-Chi Chin
CPC classification number: G03F1/64 , G03F7/2004
Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.
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Patent Agency Ranking
公开(公告)号：US10126644B2
公开(公告)日：2018-11-13
申请号：US15019478
申请日：2016-02-09
Inventor： Yu-Ching Lee , Ching-Fang Yu , Chun-Hung Lin , Ting-Hao Hsu , Ching-Hsiang Chang , Sheng-Chi Chin
Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.
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公开(公告)号：US20150104731A1
公开(公告)日：2015-04-16
申请号：US14051942
申请日：2013-10-11
Inventor： Ching-Fang Yu , Ting-Hao Hsu , Sheng-Chi Chin
IPC: G03F1/22
CPC classification number: G03F1/22
Abstract: A lithographic process will use a mask or photomask. The photomask includes a first material layer, the first material layer providing a first outer surface of the photomask. The photomask also includes a second material layer over the first material layer, the second material layer providing a second outer surface of the photomask. The two outer surfaces are substantially in parallel and a distance between the two outer surfaces along a first axis perpendicular to the two outer surfaces defines a thickness of the photomask. Also, the two outer surfaces are connected by a plurality of sides, at least one of the sides is not perpendicular to the two outer surfaces and the at least one of the sides provides substantial area for holding the lithographic photomask.
Abstract translation: 光刻工艺将使用掩模或光掩模。 光掩模包括第一材料层，第一材料层提供光掩模的第一外表面。 光掩模还包括在第一材料层上的第二材料层，第二材料层提供光掩模的第二外表面。 两个外表面基本上是平行的，沿垂直于两个外表面的第一轴线的两个外表面之间的距离限定了光掩模的厚度。 此外，两个外表面通过多个侧面连接，至少一个侧面不垂直于两个外表面，并且至少一个侧面提供用于保持光刻光掩模的实质区域。
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公开(公告)号：US20210072196A1
公开(公告)日：2021-03-11
申请号：US17102255
申请日：2020-11-23
Inventor： Jun-Hao Deng , Kuan-Wen Lin , Sheng-Chi Chin , Yu-Ching Lee
IPC: G01N29/44 , B08B13/00 , G01B17/00 , G01B21/16 , G01B17/02 , B08B3/04 , B08B5/02 , H01L21/02 , H01L21/288 , H01L21/67 , H01L21/66
Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
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公开(公告)号：US10794872B2
公开(公告)日：2020-10-06
申请号：US14942402
申请日：2015-11-16
Inventor： Jun-Hao Deng , Kuan-Wen Lin , Sheng-Chi Chin , Yu-Ching Lee
IPC: G01N29/44 , B08B13/00 , G01B17/00 , G01B21/16 , B08B3/04 , B08B5/02 , H01L21/02 , H01L21/288 , H01L21/67 , H01L21/66
Abstract: A system and method for determining clearance between a fabrication tool and a workpiece is provided. In an exemplary embodiment, the method includes receiving a substrate within a tool such that a gap is defined there between. A transducer disposed on a bottom surface of the substrate opposite the gap provides an acoustic signal that is conducted through the substrate. The transducer also receives a first echo from a top surface of the substrate that defines the gap and a second echo from a bottom surface of the tool that further defines the gap. A width of the gap is measured based on the first echo and the second echo. In some embodiments, the bottom surface of the tool is a bottom surface of a nozzle, and the nozzle provides a liquid or a gas in the gap while the transducer is receiving the first and second echoes.
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公开(公告)号：US20180348171A1
公开(公告)日：2018-12-06
申请号：US16047828
申请日：2018-07-27
Inventor： Jun-Hao Deng , Kuan-Wen Lin , Sheng-Chi Chin , Yu-Ching Lee
IPC: G01N29/44 , B08B13/00 , H01L21/02 , H01L21/66 , B08B3/04 , H01L21/67 , G01B17/00 , B08B5/02 , H01L21/288
CPC classification number: G01N29/44 , B08B3/04 , B08B5/02 , B08B13/00 , G01B17/00 , G01B21/16 , G01N2291/044 , H01L21/02041 , H01L21/02282 , H01L21/02623 , H01L21/288 , H01L21/67253 , H01L22/10
Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
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