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公开(公告)号：US09837292B2
公开(公告)日：2017-12-05
申请号：US14930032
申请日：2015-11-02
Inventor： Chun-Chih Chuang , Jung Wei Cheng , Chun-Hung Lin , Tsung-Ding Wang
CPC classification number: H01L21/67126 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
Abstract: A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package.
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公开(公告)号：US09673184B2
公开(公告)日：2017-06-06
申请号：US14609221
申请日：2015-01-29
Inventor： Yu-Chen Hsu , Chun-Hung Lin , Yu-Feng Chen , Han-Ping Pu
CPC classification number: H01L25/50 , H01L21/561 , H01L21/566 , H01L21/78 , H01L23/3128 , H01L24/08 , H01L24/14 , H01L24/16 , H01L24/80 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/08225 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/80895 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/1533 , H01L2924/181 , H01L2924/1815 , H01L2224/81 , H01L2224/80 , H01L2924/00
Abstract: A package includes a first package component having a top surface, a second package component bonded to the top surface of the first package component, and a plurality of electrical connectors at the top surface of the first package component. A molding material is over the first package component and molding the second package component therein. The molding material includes a first portion overlapping the second package component, wherein the first portion includes a first top surface, and a second portion encircling the first portion and molding bottom portions of the plurality of electrical connectors therein. The second portion has a second top surface lower than the first top surface.
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公开(公告)号：US09391012B2
公开(公告)日：2016-07-12
申请号：US14638408
申请日：2015-03-04
Inventor： Kai-Chiang Wu , Hsien-Wei Chen , Yu-Feng Chen , Chun-Hung Lin , Ming-Kai Liu , Chun-Lin Lu
IPC: H01L29/40 , H01L23/40 , H01L23/498 , H01L21/56 , H01L25/10 , H01L25/065 , H05K1/02 , H05K1/03 , H05K1/11 , H05K1/18 , H01L23/31 , H01L23/00
CPC classification number: H01L23/49838 , H01L21/4853 , H01L21/52 , H01L21/563 , H01L21/565 , H01L23/3128 , H01L23/3157 , H01L23/481 , H01L23/49811 , H01L23/49816 , H01L23/5386 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05572 , H01L2224/1132 , H01L2224/11334 , H01L2224/1144 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1712 , H01L2224/26175 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06575 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01322 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1443 , H01L2924/15311 , H01L2924/15331 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H05K1/0284 , H05K1/0313 , H05K1/111 , H05K1/181 , H05K3/40 , H05K2201/09409 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.
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公开(公告)号：US20140264849A1
公开(公告)日：2014-09-18
申请号：US14164673
申请日：2014-01-27
Inventor： Yu-Feng Chen , Han-Ping Pu , Chun-Hung Lin , Chun-Cheng Lin , Ming-Da Cheng , Kai-Chiang Wu
IPC: H01L23/00
CPC classification number: H01L23/3128 , H01L21/56 , H01L24/81 , H01L25/105 , H01L25/50 , H01L2224/131 , H01L2224/13147 , H01L2224/16237 , H01L2224/2919 , H01L2224/48227 , H01L2224/73204 , H01L2224/81815 , H01L2224/83102 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/014 , H01L2924/0665
Abstract: A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the bottom package and the printed circuit board, a first underfill layer formed between the printed circuit board and the bottom package, a semiconductor die mounted on the bottom package and a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps and the top package and the bottom package form a ladder shaped structure. The device further comprises a second underfill layer formed between the bottom package and the top package, wherein the second underfill layer is formed of a same material as the first underfill layer.
Abstract translation: 一种装置包括安装在印刷电路板上的底部封装，其中底部封装包括形成在底部封装和印刷电路板之间的多个第一凸块，形成在印刷电路板和底部封装之间的第一底部填充层， 安装在底部封装上的半导体管芯和封装在底部封装上的顶部封装，其中顶部封装包括多个第二凸起，顶部封装和底部封装形成梯形结构。 该装置还包括形成在底部封装和顶部封装之间的第二底部填充层，其中第二底部填充层由与第一底部填充层相同的材料形成。
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公开(公告)号：US20140191394A1
公开(公告)日：2014-07-10
申请号：US14204659
申请日：2014-03-11
Inventor： Chun-Hung Lin , Yu-Feng Chen , Tsung-Shu Lin , Han-Ping Pu , Hsien-Wei Chen
IPC: H01L23/00
CPC classification number: H01L24/14 , H01L23/3114 , H01L23/3171 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0233 , H01L2224/02331 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05018 , H01L2224/05024 , H01L2224/0508 , H01L2224/05085 , H01L2224/05558 , H01L2224/05569 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06135 , H01L2224/06136 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/1403 , H01L2224/14131 , H01L2224/14135 , H01L2224/14136 , H01L2224/14179 , H01L2224/16225 , H01L2224/17051 , H01L2224/81191 , H01L2224/81815 , H01L2924/00 , H01L2924/00014 , H01L2924/351 , H01L2924/3512 , H01L2924/00012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2224/05552
Abstract: A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.
Abstract translation: 芯片级半导体器件包括半导体管芯，第一突起和第二突起。 具有第一直径和第一高度的第一凸块形成在半导体管芯的外部区域上。 具有第二直径和第二高度的第二凸起形成在半导体管芯的内部区域上。 第二直径大于第一直径，而第二高度与第一高度相同。 通过改变凸块的形状，应力和应变可通过凸块重新分布。 结果，提高了芯片级半导体器件的热循环可靠性。
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Patent Agency Ranking
公开(公告)号：US20190072849A1
公开(公告)日：2019-03-07
申请号：US16181637
申请日：2018-11-06
Inventor： Yu-Ching Lee , Ching-Fang Yu , Chun-Hung Lin , Ting-Hao Hsu , Ching-Hsiang Chang , Sheng-Chi Chin
CPC classification number: G03F1/64 , G03F7/2004
Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.
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公开(公告)号：US10126644B2
公开(公告)日：2018-11-13
申请号：US15019478
申请日：2016-02-09
Inventor： Yu-Ching Lee , Ching-Fang Yu , Chun-Hung Lin , Ting-Hao Hsu , Ching-Hsiang Chang , Sheng-Chi Chin
Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.
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公开(公告)号：US20170053885A1
公开(公告)日：2017-02-23
申请号：US15346493
申请日：2016-11-08
Inventor： Chen-Shien Chen , Yu-Feng Chen , Yu-Wei Lin , Tin-Hao Kuo , Yu-Min Liang , Chun-Hung Lin
IPC: H01L23/00 , H01L21/48 , H01L23/498
CPC classification number: H01L24/16 , H01L21/481 , H01L21/4853 , H01L21/486 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/13 , H01L2224/13016 , H01L2224/13082 , H01L2224/16227 , H01L2224/16238 , H01L2224/81
Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2
Abstract translation: 一种实施方式的装置包括：管芯中的电介质层，电介质层中的导电迹线，以及导电迹线上的突起焊盘。 突起凸块至少部分地延伸在电介质层上，并且突起凸块垫包括纵向轴线和宽度方向轴线。 纵向轴线的第一尺寸与宽度方向轴线的第二尺寸的比率为约0.8至约1.2
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公开(公告)号：US20150228600A1
公开(公告)日：2015-08-13
申请号：US14175080
申请日：2014-02-07
Inventor： Chun-Hung Lin
IPC: H01L23/00 , H01L25/065 , H01L23/31 , H01L21/56 , H01L21/78
CPC classification number: H01L25/0657 , H01L21/565 , H01L21/78 , H01L21/784 , H01L23/3114 , H01L23/315 , H01L23/3192 , H01L23/562 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/73 , H01L24/92 , H01L24/94 , H01L24/96 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05569 , H01L2224/05572 , H01L2224/11009 , H01L2224/11849 , H01L2224/12105 , H01L2224/13014 , H01L2224/13016 , H01L2224/13022 , H01L2224/13023 , H01L2224/131 , H01L2224/14131 , H01L2224/14133 , H01L2224/14134 , H01L2224/14179 , H01L2224/16147 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2224/73267 , H01L2224/92125 , H01L2224/94 , H01L2225/06513 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/1032 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2924/00 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2924/00014 , H01L2924/01029
Abstract: A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.
Abstract translation: 芯片包括半导体衬底，半导体衬底上的电连接器，以及将电连接器的下部模制成型的模制复合体。 模制化合物的顶表面低于电连接器的顶端。 凹部从模塑料的顶表面延伸到模塑料中。
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公开(公告)号：US20150194379A1
公开(公告)日：2015-07-09
申请号：US14456812
申请日：2014-08-11
Inventor： Chen-Shien Chen , Yu-Feng Chen , Yu-Wei Lin , Tin-Hao Kuo , Yu-Min Liang , Chun-Hung Lin
IPC: H01L23/498 , H01L21/48
CPC classification number: H01L24/16 , H01L21/481 , H01L21/4853 , H01L21/486 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/13 , H01L2224/13016 , H01L2224/13082 , H01L2224/16227 , H01L2224/16238 , H01L2224/81
Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2
Abstract translation: 一种实施方式的装置包括：管芯中的电介质层，电介质层中的导电迹线，以及导电迹线上的突起焊盘。 突起凸块至少部分地延伸在电介质层上，并且突起凸块垫包括纵向轴线和宽度方向轴线。 纵向轴线的第一尺寸与宽度方向轴线的第二尺寸的比率为约0.8至约1.2
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