公开(公告)号：US10357867B2

公开(公告)日：2019-07-23

申请号：US15652436

申请日：2017-07-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Chi Lin ,  Kun-Tai Wu ,  You-Hua Chou ,  Chih-Tsung Lee ,  Min Hao Hong ,  Chih-Jen Wu ,  Chen-Ming Huang ,  Soon-Kang Huang ,  Chin-Hsiang Chang ,  Chih-Yuan Yang

IPC分类号： B24B37/20 ,  H01L21/673 ,  H01L21/677 ,  H01L21/66 ,  H01L21/02

摘要： A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.

公开(公告)号：US20160268192A1

公开(公告)日：2016-09-15

申请号：US15160414

申请日：2016-05-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Lin ,  Mei-Hui Fu ,  Wei-Jung Lin ,  You-Hua Chou ,  Chia-Lin Hsu ,  Hon-Lin Huang ,  Shih-Chi Lin

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3205

CPC分类号： H01L23/528 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate, a dielectric layer over the contact layer, a silicide layer over the exposed portion of the contact layer, a barrier layer along sidewalls of the opening, an alloy layer over the barrier layer, a glue layer over the alloy layer, and a conductive plug over the glue layer, wherein the dielectric layer has an opening, and the opening exposes a portion of the contact layer.

摘要翻译： 公开了互连结构和形成互连结构的方法。 互连结构包括在衬底上的接触层，接触层上的电介质层，接触层的暴露部分上的硅化物层，沿着开口侧壁的阻挡层，阻挡层上的合金层，胶 层，并且在胶层上方具有导电塞，其中介电层具有开口，并且开口暴露接触层的一部分。

公开(公告)号：US11358252B2

公开(公告)日：2022-06-14

申请号：US16515455

申请日：2019-07-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Chi Lin ,  Kun-Tai Wu ,  You-Hua Chou ,  Chih-Tsung Lee ,  Min Hao Hong ,  Chih-Jen Wu ,  Chen-Ming Huang ,  Soon-Kang Huang ,  Chin-Hsiang Chang ,  Chih-Yuan Yang

IPC分类号： B24B37/20 ,  B24B37/30 ,  H01L21/02 ,  H01L21/673 ,  H01L21/677 ,  H01L21/66

摘要： A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.

公开(公告)号：US20140264872A1

公开(公告)日：2014-09-18

申请号：US13915376

申请日：2013-06-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Lin ,  Bor-Jou Wei ,  Chun-Chang Chen ,  Yao Hsiang Liang ,  Yu-Min Chang ,  Shih-Chi Lin

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The integrated circuit structure further includes a conductive wiring in the dielectric layer. The integrated circuit structure also includes a first metallic capping layer over the conductive wiring and a second metallic capping layer over the first metallic capping layer. The second metallic capping layer has a width substantially the same as a width of the first metallic capping layer.

摘要翻译： 集成电路结构包括在半导体衬底上的半导体衬底和电介质层。 集成电路结构还包括介电层中的导电布线。 集成电路结构还包括在导电布线之上的第一金属覆盖层和在第一金属覆盖层上的第二金属覆盖层。 第二金属覆盖层具有与第一金属覆盖层的宽度基本相同的宽度。

公开(公告)号：US09718164B2

公开(公告)日：2017-08-01

申请号：US13706506

申请日：2012-12-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Chi Lin ,  Kun-Tai Wu ,  You-Hua Chou ,  Chih-Tsung Lee ,  Min Hao Hong ,  Chih-Jen Wu ,  Chen-Ming Huang ,  Soon-Kang Huang ,  Chin-Hsiang Chang ,  Chih-Yuan Yang

IPC分类号： B24B37/04 ,  B24B37/30 ,  H01L21/304 ,  H01L21/02 ,  H01L21/673 ,  H01L21/677 ,  B24B37/20 ,  H01L21/66

CPC分类号： B24B37/20 ,  H01L21/02021 ,  H01L21/02024 ,  H01L21/673 ,  H01L21/67703 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter.

公开(公告)号：US09589892B2

公开(公告)日：2017-03-07

申请号：US15160414

申请日：2016-05-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Lin ,  Mei-Hui Fu ,  Wei-Jung Lin ,  You-Hua Chou ,  Chia-Lin Hsu ,  Hon-Lin Huang ,  Shih-Chi Lin

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate, a dielectric layer over the contact layer, a silicide layer over the exposed portion of the contact layer, a barrier layer along sidewalls of the opening, an alloy layer over the barrier layer, a glue layer over the alloy layer, and a conductive plug over the glue layer, wherein the dielectric layer has an opening, and the opening exposes a portion of the contact layer.

摘要翻译： 公开了互连结构和形成互连结构的方法。 互连结构包括在衬底上的接触层，接触层上的电介质层，接触层的暴露部分上的硅化物层，沿着开口侧壁的阻挡层，阻挡层上的合金层，胶 层，并且在胶层上方具有导电塞，其中介电层具有开口，并且开口暴露接触层的一部分。

公开(公告)号：US09385080B2

公开(公告)日：2016-07-05

申请号：US14461285

申请日：2014-08-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Lin ,  Mei-Hui Fu ,  Wei-Jung Lin ,  You-Hua Chou ,  Chia-Lin Hsu ,  Hon-Lin Huang ,  Shih-Chi Lin

IPC分类号： H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer.

摘要翻译： 公开了互连结构和形成互连结构的方法。 互连结构包括在衬底上的接触层; 在所述接触层上的电介质层，其中所述电介质层具有开口，所述开口暴露所述接触层的一部分; 在接触层的暴露部分上方的硅化物层; 沿着所述开口的侧壁的阻挡层; 阻挡层上的合金层; 合金层上的胶层; 和胶层上的导电塞。

公开(公告)号：US20160049362A1

公开(公告)日：2016-02-18

申请号：US14461285

申请日：2014-08-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Lin ,  Mei-Hui Fu ,  Wei-Jung Lin ,  You-Hua Chou ,  Chia-Lin Hsu ,  Hon-Lin Huang ,  Shih-Chi Lin

IPC分类号： H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer.

摘要翻译： 公开了互连结构和形成互连结构的方法。 互连结构包括在衬底上的接触层; 在所述接触层上的电介质层，其中所述电介质层具有开口，所述开口暴露所述接触层的一部分; 在接触层的暴露部分上方的硅化物层; 沿着所述开口的侧壁的阻挡层; 阻挡层上的合金层; 合金层上的胶层; 和胶层上的导电塞。