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公开(公告)号：US20230120191A1
公开(公告)日：2023-04-20
申请号：US18086545
申请日：2022-12-21
发明人： Tin-Hao Kuo , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Yu-Chia Lai , Po-Yuan Teng
IPC分类号： H01L25/065 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/538 , H01L23/00 , H01L23/31 , H05K1/02 , H01L25/00
摘要： A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
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公开(公告)号：US11580767B2
公开(公告)日：2023-02-14
申请号：US17017640
申请日：2020-09-10
发明人： Chih-Hsuan Tai , Chih-Hua Chen , Hao-Yi Tsai , Yu-Chih Huang , Chia-Hung Liu , Ting-Ting Kuo , Ying-Cheng Tseng
摘要： A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
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公开(公告)号：US11532425B2
公开(公告)日：2022-12-20
申请号：US16734776
申请日：2020-01-06
发明人： Tzu-Sung Huang , Chen-Hua Yu , Hao-Yi Tsai , Hung-Yi Kuo , Ming Hung Tseng
IPC分类号： H01F27/42 , H01F37/00 , H01F38/00 , H01F27/28 , H02J50/80 , H02J50/10 , H01F38/14 , H01F41/04 , H01F41/10 , H01L49/02 , H01F17/00
摘要： Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.
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公开(公告)号：US11502013B2
公开(公告)日：2022-11-15
申请号：US17315735
申请日：2021-05-10
发明人： Shu-Rong Chun , Kuo Lung Pan , Tin-Hao Kuo , Hao-Yi Tsai , Pei-Hsuan Lee , Chien Ling Hwang , Yu-Chia Lai , Po-Yuan Teng , Chen-Hua Yu
IPC分类号： H01L23/32 , H01L23/538 , H01L23/31 , H01L23/00 , H01L25/065 , H01L21/56
摘要： In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
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公开(公告)号：US20220359343A1
公开(公告)日：2022-11-10
申请号：US17874293
申请日：2022-07-27
发明人： Yu-Chia Lai , Chen-Hua Yu , Chung-Shi Liu , Hsiao-Chung Liang , Hao-Yi Tsai , Chien-Ling Hwang , Kuo-Lung Pan , Pei-Hsuan Lee , Tin-Hao Kuo , Chih-Hsuan Tai
摘要： A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
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公开(公告)号：US20220352078A1
公开(公告)日：2022-11-03
申请号：US17855723
申请日：2022-06-30
发明人： Ming-Hung Tseng , Cheng-Chieh Hsieh , Hao-Yi Tsai
IPC分类号： H01L23/538 , H01L23/31 , H01L23/00
摘要： A semiconductor device includes a stacked structure, first conductive terminals and second conductive terminals. The stacked structure includes a first semiconductor component having a first area and a second semiconductor component stacked on the first semiconductor component and having a second area smaller than the first area, wherein an extending direction of the first area and an extending direction of the second area are perpendicular to a stacking direction of the first semiconductor component and the second semiconductor component. The first conductive terminals are located on the stacked structure, electrically coupled to the first semiconductor component and aside of the second semiconductor component. The second conductive terminals are located on the stacked structure and electrically coupled to the second semiconductor component.
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公开(公告)号：US20220299719A1
公开(公告)日：2022-09-22
申请号：US17206130
申请日：2021-03-19
发明人： Tsung-Yuan Yu , Hung-Yi Kuo , Cheng-Chieh Hsieh , Hao-Yi Tsai , Chung-Ming Weng , Hua-Kuei Lin , Che-Hsiang Hsu
摘要： A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.
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公开(公告)号：US20220285566A1
公开(公告)日：2022-09-08
申请号：US17750419
申请日：2022-05-23
发明人： Chih-Hsuan Tai , Hao-Yi Tsai , Yu-Chih Huang , Chih-Hao Chang , Chia-Hung Liu , Ban-Li Wu , Ying-Cheng Tseng , Po-Chun Lin
IPC分类号： H01L31/0203 , H01L31/18 , H01L31/024 , H01L31/02
摘要： A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided.
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公开(公告)号：US20220285289A1
公开(公告)日：2022-09-08
申请号：US17192897
申请日：2021-03-05
发明人： Wei-Kang Hsieh , Hao-Yi Tsai , Tin-Hao Kuo , Shih-Wei Chen
IPC分类号： H01L23/00 , H01L25/065 , H01L23/31 , H01L23/538 , H01L21/683 , H01L21/48 , H01L21/56 , H01L25/00 , H01L23/40
摘要： A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.
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公开(公告)号：US20220216103A1
公开(公告)日：2022-07-07
申请号：US17705378
申请日：2022-03-27
发明人： Po-Yuan Teng , Bor-Rung Su , De-Yuan Lu , Hao-Yi Tsai , Tin-Hao Kuo , Tzung-Hui Lee , Tai-Min Chang
IPC分类号： H01L21/768 , H01L23/48 , H01L23/31 , H01L23/00 , H01L21/027 , H01L21/56
摘要： A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.
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