公开(公告)号：US08094478B2

公开(公告)日：2012-01-10

申请号：US12878656

申请日：2010-09-09

申请人： Takaaki Furuyama ,  Makoto Niimi ,  Masahiro Niimi

发明人： Takaaki Furuyama ,  Makoto Niimi ,  Masahiro Niimi

IPC分类号： G11C5/06

CPC分类号： G11C16/12

摘要： A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

摘要翻译： 提供一种能够防止读取操作和重写操作之间的干扰并且能够防止在存储器块之间同时执行读取操作和重写操作的情况下可能发生的故障的非易失性存储器件1。 非易失性存储器件1设有多个存储体，重写控制单元2，第一电源线VCC1和第一接地线VSS1连接到该重写控制单元2，并且其适于控制相对于存储体i的重写操作， 以及连接有第二电源线VCC2和第二接地线VSS2并且适于控制相对于存储体j的读取操作的读取控制单元5，其中重写控制单元2和读取控制单元5 被布置成彼此间隔开。

公开(公告)号：US07808808B2

公开(公告)日：2010-10-05

申请号：US12177039

申请日：2008-07-21

申请人： Takaaki Furuyama ,  Makoto Niimi ,  Masahiro Niimi

发明人： Takaaki Furuyama ,  Makoto Niimi ,  Masahiro Niimi

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

摘要翻译： 提供一种能够防止读取操作和重写操作之间的干扰并且能够防止在存储器块之间同时执行读取操作和重写操作的情况下可能发生的故障的非易失性存储器件1。 非易失性存储器件1设有多个存储体，重写控制单元2，第一电源线VCC1和第一接地线VSS1连接到该重写控制单元2，并且其适于控制相对于存储体i的重写操作， 以及连接有第二电源线VCC2和第二接地线VSS2并且适于控制相对于存储体j的读取操作的读取控制单元5，其中重写控制单元2和读取控制单元5 被布置成彼此间隔开。

公开(公告)号：US5867438A

公开(公告)日：1999-02-02

申请号：US726168

申请日：1996-10-04

申请人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

发明人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

摘要： A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

摘要翻译： 具有多个存储单元的DRAM（动态随机存取存储器）包括读取或写入存储单元的数据的数据读/写电路，刷新存储在存储单元中的数据的自刷新电路，以及供给单元 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。

公开(公告)号：US5594699A

公开(公告)日：1997-01-14

申请号：US308105

申请日：1994-09-16

申请人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

发明人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

摘要： A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

摘要翻译： 具有多个存储单元的DRAM（动态随机存取存储器）包括数据读/写电路读取或写入存储单元的数据，自刷新电路刷新存储在存储单元中的数据，以及电源单元， 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。

公开(公告)号：US6097658A

公开(公告)日：2000-08-01

申请号：US189148

申请日：1998-11-10

申请人： Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

发明人： Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

摘要： A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

摘要翻译： 具有多个存储单元的DRAM（动态随机存取存储器）包括数据读/写电路读取或写入存储单元的数据，自刷新电路刷新存储在存储单元中的数据，以及电源单元， 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。

公开(公告)号：US06566937B1

公开(公告)日：2003-05-20

申请号：US10152579

申请日：2002-05-23

申请人： Katsuhiro Mori ,  Shinya Fujioka ,  Masahiro Niimi

发明人： Katsuhiro Mori ,  Shinya Fujioka ,  Masahiro Niimi

IPC分类号： H01H3776

CPC分类号： G11C17/16

摘要： Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

摘要翻译： 在第一周期的前半段通过第三开关接收到第二节点的电平时，保持电路将其作为指示保险丝的熔断状态的熔丝信号输出。 由于在第一周期的后半部分中第三开关断开，所以其后发生的第二节点的电平变化不会影响保持电路中的数据，从而防止熔丝电路的故障。 在保险丝熔断时，在第一周期之后，第一节点的电平固定在第二电源线的电平上。 这消除了保险丝两端之间的电压差，从而防止了长时间的恢复。 即使没有完全切断保险丝，也不会发生长时间退回，只有一个保险丝对保险丝电路充足。 从而缩短了在测试过程中熔断熔断器的时间。

公开(公告)号：US07564720B2

公开(公告)日：2009-07-21

申请号：US11879989

申请日：2007-07-18

申请人： Mitsuhiro Nagao ,  Masahiro Niimi ,  Kenji Nagai

发明人： Mitsuhiro Nagao ,  Masahiro Niimi ,  Kenji Nagai

IPC分类号： G11C11/03

CPC分类号： G11C16/16 ,  G11C8/16 ,  G11C11/412

摘要： A nonvolatile storage including a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.

摘要翻译： 一种非易失性存储器，包括在擦除操作中用作一个单元的多个块，并且连续执行多个擦除操作，所述非易失性存储器包括：易失性存储单元阵列，用于存储关于每个块的擦除设置信息，所述信息指示是否 其关联块是要擦除的目标; 写入放大器，用于将所述擦除设置信息写入所述易失性存储单元阵列; 第一读出放大器，用于在擦除操作开始时从易失性存储单元阵列读出目标块上的擦除设置信息; 以及第二读出放大器，用于在读出操作开始时从易失性存储单元阵列读出目标块上的擦除设置信息。

公开(公告)号：US20080049503A1

公开(公告)日：2008-02-28

申请号：US11879989

申请日：2007-07-18

申请人： Mitsuhiro Nagao ,  Masahiro Niimi ,  Kenji Nagai

发明人： Mitsuhiro Nagao ,  Masahiro Niimi ,  Kenji Nagai

IPC分类号： G11C11/34 ,  G11C16/02

CPC分类号： G11C16/16 ,  G11C8/16 ,  G11C11/412

摘要： A nonvolatile storage is disclosed which has a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.

摘要翻译： 公开了一种非易失性存储器，其具有在擦除操作中作为一个单元的多个块，并且连续执行多个擦除操作，所述非易失性存储器包括：易失性存储单元阵列，用于存储关于每个块的擦除设置信息，所述信息指示 其关联块是否是要擦除的目标; 写入放大器，用于将所述擦除设置信息写入所述易失性存储单元阵列; 第一读出放大器，用于在擦除操作开始时从易失性存储单元阵列读出目标块上的擦除设置信息; 以及第二读出放大器，用于在读出操作开始时从易失性存储单元阵列读出目标块上的擦除设置信息。

公开(公告)号：US06333890B1

公开(公告)日：2001-12-25

申请号：US09695302

申请日：2000-10-25

申请人： Masahiro Niimi ,  Shinya Fujioka ,  Tadao Aikawa ,  Yasuharu Sato

发明人： Masahiro Niimi ,  Shinya Fujioka ,  Tadao Aikawa ,  Yasuharu Sato

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18 ,  G11C8/12 ,  G11C2207/108

摘要： According to an aspect of the present invention, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area. According to the present invention, there is provided a memory device having a plurality of banks each including a plurality of memory cells, and reading or writing data from or into the memory cells in synchronism with a clock signal, the memory device comprising: a sense amplifier disposed on each of the plurality of banks, for amplifying data read from the memory cells; a plurality of common data buses shared by the plurality of banks, the number of the common data buses being less than the number of the banks; and a switching circuit disposed on each of the plurality of banks, for feeding or receiving data of the each bank to or from the plurality of common data buses; wherein read or write of data of the plurality of banks is made through successive selection of the plurality of common data buses by the switching circuit.

摘要翻译： 根据本发明的一个方面，具有多个存储体的存储器件通过使用多个公共数据总线执行存储体交织，该数据总线的数量少于存储体的数量。 本发明能够在抑制芯片面积的增加的同时更快地读取数据。 根据本发明，提供了一种具有多个存储单元的存储器件，每个存储单元包括多个存储器单元，以及与时钟信号同步地从存储器单元读取或写入数据，所述存储器件包括：感测 放大器设置在所述多个存储体中的每一个上，用于放大从所述存储器单元读取的数据; 由所述多个银行共享的多个公用数据总线，所述公共数据总线的数量小于所述存储体的数量; 以及切换电路，其设置在所述多个存储体中的每一个上，用于向所述多个公共数据总线馈送或接收每个存储体的数据; 其中通过所述切换电路连续选择所述多个公用数据总线来进行所述多个存储体的数据的读取或写入。

公开(公告)号：US08395959B2

公开(公告)日：2013-03-12

申请号：US11510061

申请日：2006-08-25

申请人： Masahiro Niimi

发明人： Masahiro Niimi

IPC分类号： G11C8/12

CPC分类号： G11C8/00 ,  G11C8/06 ,  G11C8/18

摘要： Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB) 3 is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption.

摘要翻译： 作为擦除操作的单位的存储单元区域是扇区S，读取操作和/或写入操作的单元是扇区中的块B0至B3，其中用于选择块B0至B3之一的块地址BA保存在块地址 缓冲器（BAB）3.在读取或写入操作之前执行保持操作，因此在随后的读取操作或写入操作中，不需要重新输入。 根据保持的块地址BA，选择选择信号YDn（n = 0〜3）中的任何一个，根据选择信号YDn选择任意一个块。 保持该状态，直到块地址缓冲器（BAB）3中保持的块地址BA被重写为止，因此在读取和/或写入操作的每个场合不需要进入或解码块地址BA， 访问操作可以及时，低电流消耗。