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45 条记录 (耗时 0.041 秒)

    Curable resin composition
    2.
    发明授权
    Curable resin composition 有权
    可固化树脂组合物

    公开(公告)号：US08110645B2

    公开(公告)日：2012-02-07

    申请号：US12494540

    申请日：2009-06-30

    申请人： Shigeki Mori ,  Yukihiro Nomura ,  Kazuhiro Iyo ,  Shinichi Sato

    发明人： Shigeki Mori ,  Yukihiro Nomura ,  Kazuhiro Iyo ,  Shinichi Sato

    IPC分类号： C08G77/60

    CPC分类号： C08L101/10 ,  C08G18/10 ,  C08G18/4825 ,  C08G18/4837 ,  C08G18/755 ,  C09J175/08 ,  C08G18/289

    摘要： Disclosed is a moisture-curing type curable resin composition containing: a curable resin intramolecularly having a silicon-containing functional group; and a Lewis acid or a complex of the Lewis acid as a curing catalyst, the Lewis acid being selected from the group consisting of metal halides and boron halides, which is rapidly cured at room temperature. The silicon-containing functional group is represented by general formula: —SiX1X2X3 or —SiR1X1 X2 (wherein, X1, X2 and X3 respectively represent a hydrolytic group and may be the same as or different from each other, and R1 represents a substituted or unsubstituted organic group having 1 to 20 carbons). If the silicon-containing functional group is —SiR1X1 X2, the curable resin further contains intramolecularly a polar component that is one of urethane, thiourethane, urea, thiourea, substituted urea, substituted thiourea, amide, and sulfide bonds, and hydroxyl, secondary amino and tertiary amino groups. Two-part type adhesive is constitutable with separating the curable resin from the curing catalyst.

    摘要翻译： 公开了一种湿固化型固化性树脂组合物，其含有：分子内具有含硅官能团的固化性树脂; 路易斯酸或作为固化催化剂的路易斯酸的络合物，所述路易斯酸选自金属卤化物和卤化硼，其在室温下快速固化。 含硅官能团由以下通式表示：-SiX1X2X3或-SiR1X1 X2（其中，X1，X2和X3分别表示水解基团，可以相同或不同，R1表示取代或未取代的 碳原子数为1〜20的有机基团）。 如果含硅官能团为-SiR1X1 X2，则固化性树脂还分子内含有氨基甲酸酯，硫代氨基甲酸酯，脲，硫脲，取代的脲，取代的硫脲，酰胺和硫键之一的极性成分，羟基，仲氨基 和叔氨基。 两部分型粘合剂是可固化树脂与固化催化剂分离的组成部分。

    Semiconductor memory and system apparatus
    7.
    发明申请
    Semiconductor memory and system apparatus 有权
    半导体存储器和系统装置

    公开(公告)号：US20060203576A1

    公开(公告)日：2006-09-14

    申请号：US11167318

    申请日：2005-06-28

    申请人： Koichi Nishimura ,  Shinichi Yamada ,  Yukihiro Nomura

    发明人： Koichi Nishimura ,  Shinichi Yamada ,  Yukihiro Nomura

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1045 ,  G11C11/4072 ,  G11C2029/0407

    摘要： A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode register outputs a soft reset signal when at least a value of one-bit of the register part represents a reset state. A reset signal generator outputs a reset signal for resetting an internal circuit in response to the soft reset signal. In the present invention, a system that controls the semiconductor memory is required to necessarily assign a predetermined bit with a setting command of the mode register in order to generate the soft reset signal. Accordingly, it is possible to reliably reset the internal circuit by external control.

    摘要翻译： 模式寄存器的寄存器部分具有多个操作设置部分，其中分别设置多种类型的操作规范以操作半导体存储器。 当至少寄存器部分的1位的值表示复位状态时，模式寄存器输出软复位信号。 复位信号发生器响应于软复位信号输出用于复位内部电路的复位信号。 在本发明中，控制半导体存储器的系统需要用模式寄存器的设定命令来分配预定的位，以产生软复位信号。 因此，可以通过外部控制可靠地复位内部电路。

    Self-test circuit and memory device incorporating it
    8.
    发明授权
    Self-test circuit and memory device incorporating it 有权
    自检电路和结合其的存储器件

    公开(公告)号：US06907555B1

    公开(公告)日：2005-06-14

    申请号：US09691115

    申请日：2000-10-19

    申请人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

    发明人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F12/16 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/12 ,  G11C29/44

    CPC分类号： G11C29/44

    摘要： The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.

    摘要翻译： 本发明是一种结合在存储器件中的自检电路（BIST），其响应于来自外部的测试激活信号被激活。 当该自检电路响应于来自外部的测试激活信号（WBIZ）被激活时，它产生测试操作命令（WBI-CMD），生成测试地址（WBI-ADD），并生成测试数据（WBI- 数据）。 此外，在自检电路将测试数据写入存储单元之后，进行比较以确定从该存储单元读取的读取数据是否与写入的测试数据相同并存储信息 关于这个比较的结果。 然后将该比较结果信息输出到外部。

    Semiconductor integrated circuit device having built-in step-down circuit for stepping down external power supply voltage
    10.
    发明授权
    Semiconductor integrated circuit device having built-in step-down circuit for stepping down external power supply voltage 失效
    具有降低外部电源电压的内置降压电路的半导体集成电路装置

    公开(公告)号：US5675280A

    公开(公告)日：1997-10-07

    申请号：US654786

    申请日：1996-05-28

    申请人： Yukihiro Nomura ,  Shigemasa Ito

    发明人： Yukihiro Nomura ,  Shigemasa Ito

    IPC分类号： G05F3/24 ,  G05F1/46 ,  G11C11/401 ,  G11C11/407 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  G05F3/02

    CPC分类号： G05F1/465 ,  G05F3/247

    摘要： An LSI device can provide a desired constant value of a step-down voltage even if there are variations due to the production processes and a stable characteristic of internal circuits is obtained. The LSI device such as a DRAM includes a first input terminal of the high-voltage-side external supply voltage, a constant current source and a second input terminal of the low-voltage-side supply voltage. Further, the device includes a circuit which makes a voltage between two terminals variable due to the disconnection of each fuse. A step-down circuit is formed by the constant current source and the load circuit and provides a step-down voltage V.sub.B for stepping down the external supply voltage V.sub.CC.

    摘要翻译： 即使由于生产过程而产生变化，LSI器件也能够提供所需的降压电压恒定值，并获得内部电路的稳定特性。 诸如DRAM的LSI器件包括高电压侧外部电源电压的第一输入端子，恒定电流源和低压侧电源电压的第二输入端子。 此外，该装置包括使两个端子之间的电压由于每个保险丝断开而变化的电路。 降压电路由恒流源和负载电路形成，并提供用于降低外部电源电压VCC的降压电压VB。