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1.发明申请PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 有权图案生成方法，制造半导体器件的方法和计算机程序产品公开(公告)号：US20100241261A1
公开(公告)日：2010-09-23
申请号：US12705640
申请日：2010-02-15
申请人： Takafumi TAGUCHI , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
发明人： Takafumi TAGUCHI , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
CPC分类号： G03F1/36
摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.
摘要翻译： 基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据执行模式形成模拟。 根据模拟结果提取的风险点计算过程条件的最差条件。 改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度 小于模拟结果。
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2.发明申请METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND COMPUTER READABLE MEDIUM FOR STORING PATTERN SIZE SETTING PROGRAM 有权制造半导体器件的方法和用于存储图案尺寸设置程序的计算机可读介质公开(公告)号：US20120184109A1
公开(公告)日：2012-07-19
申请号：US13397750
申请日：2012-02-16
IPC分类号： H01L21/302
CPC分类号： H01L21/0337
摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.
摘要翻译： 通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸 在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。
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3.发明申请DESIGN LAYOUT DATA CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开设计布局数据创建方法，计算机程序产品和制造半导体器件的方法公开(公告)号：US20100003819A1
公开(公告)日：2010-01-07
申请号：US12491129
申请日：2009-06-24
CPC分类号： H01L27/0207 , G06F17/5068 , G06F2217/12 , H01L27/118 , Y02P90/265
摘要： A design layout data creating method includes creating design layout data of a semiconductor device such that patterns formed on a wafer when patterns corresponding to the design layout data are formed on the wafer have a pattern coverage ratio within a predetermined range in a wafer surface and total peripheral length of the patterns formed on the wafer when the patterns corresponding to the design layout are formed on the wafer is pattern peripheral length within a predetermined range.
摘要翻译： 设计布局数据创建方法包括：创建半导体器件的设计布局数据，使得当在晶片上形成对应于设计布局数据的图案时，在晶片上形成的图案具有在晶片表面的预定范围内的图案覆盖率，并且总计 当在晶片上形成对应于设计布局的图案时，在晶片上形成的图案的周长长度在预定范围内。
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4.发明申请MASK INSPECTION METHOD, MASK PRODUCTION METHOD, SEMICONDUCTOR DEVICE PRODUCTION METHOD, AND MASK INSPECTION DEVICE 审中-公开掩模检查方法，掩模生产方法，半导体器件生产方法和掩模检测装置公开(公告)号：US20120311511A1
公开(公告)日：2012-12-06
申请号：US13399042
申请日：2012-02-17
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70 , G06F17/5009
摘要： A mask inspection method according to the embodiments, original data corresponding to a semiconductor integrated circuit pattern to be formed on a substrate is created. After that, original production simulation which mocks an original production process is performed on the original data to derive information relating to an original pattern shape in the case of forming an original pattern corresponding to the original data on an original. After that, whether or not the information relating to an original pattern shape satisfies a predetermined value decided based on the original production process is determined.
摘要翻译： 根据实施例的掩模检查方法，产生对应于要形成在基板上的半导体集成电路图案的原始数据。 之后，对原始数据执行原始制作过程的原始制作模拟，以在形成与原始数据相对应的原始图案的情况下导出与原始图案形状有关的信息。 之后，确定与原始图案形状相关的信息是否满足基于原始制作处理决定的预定值。
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公开(公告)号：US20110307845A1
公开(公告)日：2011-12-15
申请号：US13050864
申请日：2011-03-17
申请人： Takafumi TAGUCHI , Toshiya KOTANI , Hiromitsu MASHITA , Fumiharu NAKAJIMA , Ryota ABURADA , Chikaaki KODAMA
发明人： Takafumi TAGUCHI , Toshiya KOTANI , Hiromitsu MASHITA , Fumiharu NAKAJIMA , Ryota ABURADA , Chikaaki KODAMA
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.
摘要翻译： 根据一个实施例的图案尺寸计算方法计算当在形成在基板上的电路图案的上层中处理电路图案时用作掩模的掩模构件的锥形形状。 该方法基于锥形形状从电路图案上的形状预测位置计算面向掩模构件的打开角度。 该方法根据在形状预测位置处形成的打开角度来计算电路图案的尺寸。
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6.发明申请NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开非易失性半导体存储器件及其制造方法公开(公告)号：US20110069531A1
公开(公告)日：2011-03-24
申请号：US12858986
申请日：2010-08-18
CPC分类号： H01L27/2481 , G11C5/02 , G11C11/161 , G11C11/1659 , G11C11/22 , G11C13/0004 , H01L27/0203 , H01L27/0207 , H01L27/1021 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/1675
摘要： According to one embodiment, a method of manufacturing a nonvolatile semiconductor storage device includes a memory-cell forming step, a first wire forming step, and a second wire forming step. The memory-cell forming step is forming dummy memory cells arranged at a predetermined space apart from an end memory cell located at an end of a group of memory cells set in contact with the same first or second wire among the memory cells, the dummy memory cells having a laminated structure same as that of the memory cells and being set in contact with no second wire.
摘要翻译： 根据一个实施例，制造非易失性半导体存储装置的方法包括存储单元形成步骤，第一线形成步骤和第二线形成步骤。 存储单元形成步骤是形成布置在与存储单元中的与相同的第一或第二布线接触的一组存储单元的一端的端部存储单元隔开的预定空间的虚拟存储单元，该虚拟存储器 电池具有与存储单元的层叠结构相同的层叠结构，并与第二导线接触。
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公开(公告)号：US20100266960A1
公开(公告)日：2010-10-21
申请号：US12721310
申请日：2010-03-10
申请人： Hiromitsu MASHITA , Toshiya KOTANI , Michiya TAKIMOTO , Hidefumi MUKAI , Takafumi TAGUCHI , Kazuya FUKUHARA
发明人： Hiromitsu MASHITA , Toshiya KOTANI , Michiya TAKIMOTO , Hidefumi MUKAI , Takafumi TAGUCHI , Kazuya FUKUHARA
CPC分类号： G03B27/42 , G03F7/70525 , G03F7/70625
摘要： A method of manufacturing a semiconductor device according to an embodiment includes determining a second exposure parameter including exposure parameters except for an exposure amount from a dimension distribution information so that a resist pattern of a first resist pattern formed based on a second pattern has a desired dimension in a plurality of regions to be shot within a surface of a wafer.
摘要翻译： 根据实施例的制造半导体器件的方法包括从尺寸分布信息确定包括曝光量除外的曝光参数的第二曝光参数，使得基于第二图案形成的第一抗蚀剂图案的抗蚀剂图案具有期望的尺寸 在要在晶片表面内拍摄的多个区域中。
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8.发明申请RUBBER COMPOSITION FOR TREAD, METHOD FOR PRODUCING THE SAME, AND HEAVY-LOAD TIRE 有权用于TREAD的橡胶组合物，用于生产它们的方法和重负荷轮胎公开(公告)号：US20130030083A1
公开(公告)日：2013-01-31
申请号：US13560090
申请日：2012-07-27
申请人： Takafumi TAGUCHI , Naoya Ichikawa
发明人： Takafumi TAGUCHI , Naoya Ichikawa
CPC分类号： C08C1/04 , B60C1/0016 , C08C1/15 , C08L7/00 , C08L15/00 , Y02T10/862 , Y10T152/10 , C08L9/00
摘要： The present invention provides a rubber composition for a tread which enables improvement in fuel economy, breaking performance, and abrasion resistance in a balanced manner; a method for producing the rubber composition; and a heavy-load tire. The present invention relates to a rubber composition for a tread of a heavy-load tire, including a modified natural rubber having a phosphorus content of 200 ppm or less, and carbon black.
摘要翻译： 本发明提供一种用于胎面的橡胶组合物，其能够以均衡的方式提高燃料经济性，断裂性能和耐磨性; 橡胶组合物的制造方法; 和一个重载轮胎。 本发明涉及一种重载轮胎的胎面用橡胶组合物，其包含磷含量为200ppm以下的改性天然橡胶和炭黑。
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