公开(公告)号：US5554881A

公开(公告)日：1996-09-10

申请号：US357492

申请日：1994-12-15

申请人： Takahisa Koyasu ,  Kouji Numazaki ,  Hirokazu Kasuya ,  Mitsuhiro Saitou ,  Kazuhisa Ikeda

发明人： Takahisa Koyasu ,  Kouji Numazaki ,  Hirokazu Kasuya ,  Mitsuhiro Saitou ,  Kazuhisa Ikeda

IPC分类号： H01L23/485 ,  H01L29/70

CPC分类号： H01L24/05 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4823 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043

摘要： At least four electrodes are provided on the same surface of a discrete transistor. Among these electrodes, one electrode is set as a base electrode, an electrode neighboring the base electrode in the up-and-down direction is set as an emitter electrode and an electrode neighboring the base electrode in the right-and-left direction is set as a collector electrode. On the same surface, a base electrode is provided at a position which is neither in the up-and-down direction nor in the right-and-left direction with respect to the base electrode. When the discrete transistor having this type of electrode arrangement is mounted on a substrate, one of the base electrodes formed on the substrate is connected to a first wiring, the collector electrode is connected to a second wiring, and the emitter electrode is connected to a third wiring.

摘要翻译： 在分立晶体管的同一表面上设置至少四个电极。 在这些电极中，将一个电极设置为基极，将与上下方向的基极相邻的电极设定为发射电极，并且设定与左右方向的基极相邻的电极 作为集电极。 在相同的表面上，基极相对于基极设置在既不在上下方向也不在左右方向上的位置。 当具有这种类型的电极布置的分立晶体管安装在基板上时，形成在基板上的一个基极连接到第一布线，集电极连接到第二布线，并且发射极连接到 第三线。

公开(公告)号：US5917246A

公开(公告)日：1999-06-29

申请号：US620580

申请日：1996-03-22

申请人： Hirokazu Kasuya ,  Kouji Numazaki ,  Takahisa Koyasu ,  Mitsuhiro Saitou

发明人： Hirokazu Kasuya ,  Kouji Numazaki ,  Takahisa Koyasu ,  Mitsuhiro Saitou

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/24 ,  H01L23/29 ,  H01L23/31 ,  H05K3/28 ,  H05K3/34

CPC分类号： H01L23/24 ,  H01L21/56 ,  H01L2224/45144 ,  H01L2224/48091 ,  H05K3/284 ,  H05K3/3405

摘要： A semiconductor package, which secures the protection of circuit elements from the external environment, is disclosed. A single in-line package (SIP) is constructed by fixingly sealing a hybrid integrated circuit component within a casing with epoxy resin. A sleeve is bonded on the surface of a ceramic substrate. The sleeve is formed with silicon rubber into a pocket shape so as to cover respective circuit elements of the hybrid integrated circuit component. In the sleeve is made an opening part. Silicon gel is poured into the sleeve as a fixingly sealing material and cured to seal the respective circuit elements. Terminals downwardly extends in parallel with each other from an end part of the ceramic substrate through an opening part of the casing.

摘要翻译： 公开了一种确保电路元件与外部环境的保护的半导体封装。 单个在线封装（SIP）是通过将环形树脂固定密封在壳体内的混合集成电路部件构成的。 套筒结合在陶瓷基板的表面上。 套筒由硅橡胶形成为袋形，以覆盖混合集成电路部件的各个电路元件。 在袖子里打开了一部分。 将硅胶作为固定密封材料倒入套筒中并固化以密封各个电路元件。 端子从陶瓷基板的端部通过壳体的开口部向下平行地延伸。

公开(公告)号：US5739546A

公开(公告)日：1998-04-14

申请号：US666646

申请日：1996-06-18

申请人： Mitsuhiro Saitou ,  Kouji Numazaki ,  Hiroyuki Ban

发明人： Mitsuhiro Saitou ,  Kouji Numazaki ,  Hiroyuki Ban

IPC分类号： H01L21/66 ,  H01L21/822 ,  H01L23/528 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10

CPC分类号： H01L22/32 ,  H01L23/5286 ,  H01L27/0218 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A semiconductor wafer, having a relatively wide power supply line and ground line, and which can also prevent short-circuiting between these lines. Multiple integrated circuit formation regions, whereon integrated circuits have been formed, are disposed on a semiconductor wafer. A silicon oxide film is formed on a silicon substrate, and a ground line conductor is formed on the silicon oxide film. This ground line conductor is extended over scribe lines. A layer insulation film composed of silicon oxide film is deposited on the silicon oxide film with the ground line conductor interposed therebetween, and a power supply line conductor is formed on the layer insulation film to overlap the ground line conductor. The power supply line conductor is extended over scribe lines. In the integrated circuit formation regions, a power supply pad and the power supply line conductor are electrically connected. A ground pad and the ground line conductor are also electrically connected.

摘要翻译： 具有相对宽的电源线和接地线的半导体晶片，并且还可以防止这些线之间的短路。 多个集成电路形成区域已经形成集成电路，被布置在半导体晶片上。 在硅衬底上形成氧化硅膜，在氧化硅膜上形成接地线导体。 该接地线导体在划线上延伸。 在氧化硅膜上沉积由氧化硅膜构成的层绝缘膜，其间插入有接地线导体，并且在该层绝缘膜上形成与该接地线导体重叠的电源线导体。 电源线导体在划线上延伸。 在集成电路形成区域中，电源焊盘和电源线导体电连接。 接地焊盘和接地线导体也电连接。