公开(公告)号：US07840727B2

公开(公告)日：2010-11-23

申请号：US11491919

申请日：2006-07-25

申请人： Takanori Saeki ,  Yasushi Aoki ,  Masatomo Eimitsu ,  Masashi Nakagawa ,  Minoru Nishizawa ,  Tadashi Iwasaki ,  Koichiro Kiguchi

发明人： Takanori Saeki ,  Yasushi Aoki ,  Masatomo Eimitsu ,  Masashi Nakagawa ,  Minoru Nishizawa ,  Tadashi Iwasaki ,  Koichiro Kiguchi

IPC分类号： G06F13/12 ,  G06F9/44

CPC分类号： G06F13/4018 ,  Y02D10/14 ,  Y02D10/151

摘要： Disclosed is a serial-to-parallel converter/parallel-to-serial converter/FIFO unified circuit which includes a register, a selector and a counter. The register receives serial input data and converts the serial data into parallel data based on frequency-divided multi-phase clock signals from a counter. The selector receives the parallel data from the register to select one of the data in accordance with a control signal. The counter generates the control signal for the selector so that plural items of data will be output serially from the selector in the sequence in which the plural items data have been serially supplied to the register.

摘要翻译： 公开了一种串并转换器/并 - 串转换器/ FIFO统一电路，其包括寄存器，选择器和计数器。 寄存器接收串行输入数据，并根据来自计数器的分频多相时钟信号将串行数据转换为并行数据。 选择器从寄存器接收并行数据，以根据控制信号选择一个数据。 计数器产生用于选择器的控制信号，使得多个数据项目将从串行提供给寄存器的顺序从选择器串行地输出。

公开(公告)号：US07800918B2

公开(公告)日：2010-09-21

申请号：US11145009

申请日：2005-06-06

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： G11C5/066 ,  G06F13/1684 ,  G11C5/04 ,  H05K1/14 ,  H05K1/141 ,  H05K3/366 ,  H05K2201/045 ,  H05K2201/10159 ,  Y02D10/14

摘要： There is provided a memory module that facilitates meeting the needs of high-speed performance and large capacity. It comprises first module substrates (101 through 108), each with multiple DRAM devices (11), and a second module substrate whereon the first modules (101 through 108) are mounted, signal line groups connected to the multiple first modules respectively are provided in parallel, and a controller LSI (50), connected to the multiple first modules respectively via the signal line groups provided in parallel, that converts the signal lines into fewer signal lines than the total number of the signal line groups and outputs the result is provided, and the second module substrate (20) is mounted on a motherboard (40).

摘要翻译： 提供了一个可以满足高速性能和大容量需求的内存模块。 它包括第一模块基板（101至108），每个具有多个DRAM器件（11）以及第一模块（101至108）安装在其上的第二模块基板，分别连接到多个第一模块的信号线组分别设置在 并联的控制器LSI（50），分别经由并联设置的信号线组连接到多个第一模块，将信号线转换成比信号线组的总数少的信号线，并输出结果 ，并且第二模块基板（20）安装在母板（40）上。

公开(公告)号：US20090102532A1

公开(公告)日：2009-04-23

申请号：US12232071

申请日：2008-09-10

申请人： Masatomo Eimitsu ,  Takanori Saeki

发明人： Masatomo Eimitsu ,  Takanori Saeki

IPC分类号： H03K3/356 ,  H03K3/00

CPC分类号： H03K3/356121 ,  H03K3/0375 ,  H03K3/356156

摘要： A latch circuit includes: a first terminal; a second terminal; a first data-gating circuit coupled to the first terminal and the second terminal, the first data-gating circuit non-reversely gating the second signal in response to the first signal to reveal a third signal; a second data-gating circuit coupled to the first terminal and the second terminal, the second data-gating circuit reversely gating the second signal in response to the first signal to reveal a fourth signal; a third terminal receiving a fifth signal; a selector circuit coupled to the first data-gating circuit and the second data-gating circuit, the selector circuit outputting one of the third signal and the fourth signal in response to the fifth signal to latch one of the third signal and the fourth signal, respectively; and a bistable circuit coupled to the selector circuit, the bistable circuit holding one of the third signal and the fourth signal.

摘要翻译： 锁存电路包括：第一端子; 第二个终端 耦合到第一端子和第二端子的第一数据选通电路，第一数据选通电路响应于第一信号而不反向选通第二信号以显示第三信号; 耦合到第一端子和第二端子的第二数据门控电路，第二数据选通电路响应于第一信号反向选通第二信号以显示第四信号; 接收第五信号的第三终端; 选择器电路，耦合到第一数据选通电路和第二数据选通电路，选择器电路响应于第五信号输出第三信号和第四信号之一，以锁存第三信号和第四信号之一， 分别; 以及耦合到所述选择器电路的双稳态电路，所述双稳态电路保持所述第三信号和所述第四信号之一。

公开(公告)号：US20080105929A1

公开(公告)日：2008-05-08

申请号：US11902391

申请日：2007-09-21

申请人： Masatomo Eimitsu ,  Takanori Saeki

发明人： Masatomo Eimitsu ,  Takanori Saeki

IPC分类号： H01L27/088

CPC分类号： H01L27/11807 ,  H01L27/0207 ,  Y10S257/909 ,  Y10S257/919

摘要： According to an aspect of the present invention, there is provided a semiconductor IC that includes a plurality of standard cells arranged in a first direction on a semiconductor substrate, and a first diffusion layer connected to a first power source and a second diffusion layer connected to a second power source in the each standard cell, wherein the first diffusion layers as well as the second diffusion layers of neighboring standard cells are integrally formed.

摘要翻译： 根据本发明的一个方面，提供了一种半导体IC，其包括在半导体衬底上沿第一方向布置的多个标准单元，以及连接到第一电源的第一扩散层和连接到 在每个标准单元中的第二电源，其中相邻标准单元的第一扩散层以及第二扩散层是一体形成的。

公开(公告)号：US07345602B2

公开(公告)日：2008-03-18

申请号：US11493602

申请日：2006-07-27

申请人： Takanori Saeki ,  Yasushi Aoki ,  Tadashi Iwasaki ,  Toshihiro Narisawa ,  Makoto Tanaka ,  Yoichi Iizuka ,  Nobuhiro Ooki

发明人： Takanori Saeki ,  Yasushi Aoki ,  Tadashi Iwasaki ,  Toshihiro Narisawa ,  Makoto Tanaka ,  Yoichi Iizuka ,  Nobuhiro Ooki

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.

摘要翻译： 公开了一种包括第一并行转换器，第二并行到串行转换器，混合电路和时钟发生电路的预加重电路。 第一个并行到串行转换器将并行数据转换为第一个串行数据，第二个并行到串行转换器将并行数据转换成第二个串行数据。 混合电路从第一并行转换器接收第一串行数据和来自第二并行 - 串行转换器的第二串行数据，以输出强调第一串行数据的变化点的信号。 时钟发生电路分别输出由具有相互不同相位的时钟构成的第一组时钟和由具有相互不同相位的时钟组成的第二组时钟，分别与第一和第二并行 - 串行转换器。 第二组时钟的第一相位时钟对应于第一组时钟的第二相位时钟。

公开(公告)号：US07071755B2

公开(公告)日：2006-07-04

申请号：US10844555

申请日：2004-05-13

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： H03K3/00 ,  G06F1/04

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K5/133 ,  H03K5/14 ,  H04L7/0337

摘要： A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

公开(公告)号：US20050104638A1

公开(公告)日：2005-05-19

申请号：US11022653

申请日：2004-12-28

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03H11/26 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H04L7/00 ,  H04L7/033 ,  H03L7/06

CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00052

摘要： A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.

摘要翻译： 用于减少抖动的时钟控制电路具有至少一个平均电路，用于产生并从输出端输出具有时间差的信号，所述时间差是通过对分别从第一和第二输入端子输入的第一和第二信号之间的时间差内部进行分频而得到的。 第一和第二时钟信号被分别提供给定时平均电路的第一和第二输入端，并且产生其中平均了第一和第二时钟信号的脉冲之间的时间差的时钟。

公开(公告)号：US06771107B2

公开(公告)日：2004-08-03

申请号：US10330275

申请日：2002-12-30

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： H03K300

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K5/133 ,  H03K5/14 ,  H04L7/0337

摘要： A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

公开(公告)号：US06509775B2

公开(公告)日：2003-01-21

申请号：US09799543

申请日：2001-03-05

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： H03H1126

CPC分类号： H03K5/133 ,  H03K5/135

摘要： A synchronous delay circuit apparatus include two sets of synchronous delay circuits 100, 101 each including a first delay circuit chain for period measurement in which input clocks propagate and a second delay circuit chain for period reproduction and delay detection circuits 5, 7 for detecting the propagation delay time caused in propagating clocks from an input node to an output node of a clock propagation path to issue a control signal for halting propagation of the input clock signals to the respective synchronous delay circuits. A delay circuit 6 is introduced in an input of at least one of the delay detection circuits to differentiate a delay time detected in one delay detection circuit 7 from a delay time detected by the other delay detection circuit 5 to differentiate detected period from the delay detected in the other delay detection circuit 5. Even when the propagation delay time in the clock propagation path 4 becomes longer or shorter than the clock period, no discontinuity in the clocks supplied from the synchronous delay circuit to the clock propagation path.

摘要翻译： 同步延迟电路装置包括两组同步延迟电路100,101，每组包括输入时钟传播的周期测量的第一延迟电路链和用于周期再现的第二延迟电路链和用于检测传播的延迟检测电路5,7 在从时钟传播路径的输入节点向输出节点传播时钟时产生的延迟时间，以发出用于停止输入时钟信号传播到各个同步延迟电路的控制信号。 延迟电路6被引入至少一个延迟检测电路的输入，以将在一个延迟检测电路7中检测的延迟时间与由另一个延迟检测电路5检测到的延迟时间区分开来，以将检测到的周期与检测到的延迟区分开来 即使当时钟传播路径4中的传播延迟时间变得比时钟周期长或短时，从同步延迟电路向时钟传播路径提供的时钟没有不连续性。

公开(公告)号：US06388490B2

公开(公告)日：2002-05-14

申请号：US09810203

申请日：2001-03-19

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： H03H1126

CPC分类号： H03K5/131 ,  H03K2005/00071

摘要： Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.

摘要翻译： 公开了一种时钟周期检测电路，其中可以通过预先执行粗略的周期调整来扩大相位调整和倍频器电路等的工作范围。 具有稍微重叠的操作范围和不同操作中心的多个延迟感测电路相对于通过延迟感测电路的输入时钟信号并联连接。 使用识别时钟信号经过的延迟感测电路的信号和时钟信号未通过的延迟感测电路，在短时间内粗略地感测时钟周期。