公开(公告)号：US4611335A

公开(公告)日：1986-09-09

申请号：US422190

申请日：1982-09-23

申请人： Takao Arai ,  Masaharu Kobayashi ,  Takashi Takeuchi ,  Eiji Okubo ,  Hiroshi Endoh

发明人： Takao Arai ,  Masaharu Kobayashi ,  Takashi Takeuchi ,  Eiji Okubo ,  Hiroshi Endoh

IPC分类号： G11B20/10 ,  G11B20/14 ,  H04L7/033 ,  H04L7/04 ,  H04L7/02

CPC分类号： G11B20/1403 ,  G11B20/10527 ,  H04L7/0331 ,  H04L7/042

摘要： A circuit for reproducing a signal associated with synchronization with a digital data signal. The digital data signal includes a combination of a plurality of pulses each having a predetermined pulse width. The reproducing circuit comprises a logic circuit for discriminating the pulse width of at least one of the plurality of pulses, an oscillator and a frequency divider connected with the oscillator and responsive to the output of the logic circuit to generate a clock signal timed with the output of the logic circuit.

摘要翻译： 一种用于再现与数字数据信号同步的信号的电路。 数字数据信号包括具有预定脉冲宽度的多个脉冲的组合。 再现电路包括用于鉴别多个脉冲中的至少一个脉冲的脉冲宽度的逻辑电路，与振荡器连接的振荡器和分频器，并且响应逻辑电路的输出以产生与输出定时的时钟信号 的逻辑电路。

公开(公告)号：USRE34295E

公开(公告)日：1993-06-29

申请号：US486389

申请日：1990-02-28

申请人： Toshifumi Shibuya ,  Hiroshi Endoh ,  Yoshimi Iso ,  Takao Arai ,  Hiroo Okamoto

发明人： Toshifumi Shibuya ,  Hiroshi Endoh ,  Yoshimi Iso ,  Takao Arai ,  Hiroo Okamoto

IPC分类号： H03M1/00

CPC分类号： H03M1/504 ,  H03M1/822

摘要： An integration type D/A and A/D converter having improved linearity and low power consumption. Logic circuits such as ECL counters consuming a major part of power of the D/A and A/D converters are realized through CMOS process. Current source circuits, current switch circuit and comparator circuit of the integration type A/D converter are realized in IC through bipolar process ensuring high accuracy and low noise. Logic parts such as counter is realized through CMOS process.

公开(公告)号：US4780772A

公开(公告)日：1988-10-25

申请号：US902562

申请日：1986-09-02

申请人： Toshifumi Shibuya ,  Takao Arai ,  Hiroshi Endoh

发明人： Toshifumi Shibuya ,  Takao Arai ,  Hiroshi Endoh

IPC分类号： G11B5/008 ,  G11B7/005 ,  G11B15/18 ,  G11B19/247 ,  G11B20/10 ,  G11B27/00 ,  G11B5/02 ,  G11B5/09

CPC分类号： G11B15/1875 ,  G11B19/247 ,  G11B20/10527 ,  G11B27/005 ,  G11B5/0086 ,  G11B7/005 ,  G11B2220/20 ,  G11B2220/2545 ,  G11B2220/90 ,  G11B2220/913

摘要： A digital signal reproducing apparatus in which the frequency of a basic clock signal generated from a clock generator having a fixed oscillation frequency is divided to produce a clock signal used for processing a digital signal, and, when the transmission speed of the digital signal is changed, the frequency division ratio is also changed to produce a clock signal synchronous with the digital signal transmitted at the changed transmission speed.

摘要翻译： 一种数字信号再现装置，其中从具有固定振荡频率的时钟发生器产生的基本时钟信号的频率被分频以产生用于处理数字信号的时钟信号，并且当数字信号的传输速度改变时 ，分频比也被改变，以产生与以改变的传输速度传输的数字信号同步的时钟信号。

公开(公告)号：US4746900A

公开(公告)日：1988-05-24

申请号：US938965

申请日：1986-12-08

申请人： Toshifumi Shibuya ,  Hiroshi Endoh ,  Yoshimi Iso ,  Takao Arai ,  Hiroo Okamoto

发明人： Toshifumi Shibuya ,  Hiroshi Endoh ,  Yoshimi Iso ,  Takao Arai ,  Hiroo Okamoto

IPC分类号： H03M1/00 ,  H03M1/50

CPC分类号： H03M1/504 ,  H03M1/822

摘要： An integration type D/A and A/D converter having improved linearity and low power consumption. Logic circuits such as ECL counters consuming a major part of power of the D/A and A/D converters are realized through CMOS process. Current source circuits, current switch circuit and comparator circuit of the integration type A/D converter are realized in IC through bipolar process ensuring high accuracy and low noise. Logic parts such as counter is realized through CMOS process.

摘要翻译： 具有改善的线性度和低功耗的积分型D / A和A / D转换器。 通过CMOS工艺实现了消耗D / A和A / D转换器大部分功耗的ECL计数器的逻辑电路。 集成型A / D转换器的电流源电路，电流开关电路和比较电路通过双极工艺在IC中实现，确保了高精度和低噪声。 逻辑部件如计数器通过CMOS工艺实现。

公开(公告)号：US4937686A

公开(公告)日：1990-06-26

申请号：US929909

申请日：1986-11-13

申请人： Takao Arai ,  Masaharu Kobayashi ,  Nobutaka Amada ,  Yasufumi Yumde ,  Hiroaki Takahashi

发明人： Takao Arai ,  Masaharu Kobayashi ,  Nobutaka Amada ,  Yasufumi Yumde ,  Hiroaki Takahashi

IPC分类号： G11B20/10 ,  G11B20/18 ,  H04N5/928

CPC分类号： H04N5/928 ,  G11B20/10527 ,  G11B20/1809 ,  G11B2020/1087

摘要： A PCM audio signal recording and reproducing apparatus samples an audio signal with a sampling frequency having an asynchronous relation to a field frequency of a video signal; converts it to a PCM signal, adds error detection/correction data to a predetermined number of PCM data, forms a data frame by those signals, modulates it in accordance with a predetermined modulation system, and records the audio signal together with the video signal or just the audio signal on a record medium by using a rotary head type scanner which is controlled so as to have a synchronous relation to the field frequency of the video signal. A digital signal processing circuit having a memory of a predetermined capacity is provided, and the number of digital data to be recorded in one data frame is varied in accordance with a difference between the number of input data of the digital audio signal to the digital signal processing circuit and the number of output data supplied to the record medium for recording. In the recording mode, the PCM audio signal is sectioned into blocks, a data block address signal is added to each block to indicate a relative order of a block to the other blocks and is completely added in one track, certain number of blocks are combined to form a block set for processing signals, and an identification signal completing in the block and an interleave block address signal for indicating a relative order to other blocks are added to each block.

摘要翻译： PCM音频信号记录和再现装置以与视频信号的场频率具有异步关系的采样频率对音频信号进行采样; 将其转换为PCM信号，将错误检测/校正数据添加到预定数量的PCM数据，通过这些信号形成数据帧，根据预定的调制系统对其进行调制，并将音频信号与视频信号一起记录或 通过使用被控制为与视频信号的场频率具有同步关系的旋转头型扫描仪，仅在记录介质上的音频信号。 提供具有预定容量的存储器的数字信号处理电路，并且要记录在一个数据帧中的数字数据的数量根据数字音频信号的输入数据数与数字信号之间的差异而变化 处理电路和提供给用于记录的记录介质的输出数据的数量。 在记录模式下，将PCM音频信号分割为块，将数据块地址信号添加到每个块，以指示块与其他块的相对顺序，并将其完全添加到一个轨道中，将一定数量的块组合 形成用于处理信号的块集合，并且在块中完成的识别信号和用于指示其他块的相对顺序的交织块地址信号被添加到每个块。

公开(公告)号：US4670796A

公开(公告)日：1987-06-02

申请号：US625235

申请日：1984-06-27

申请人： Masaharu Kobayashi ,  Takaharu Noguchi ,  Takao Arai ,  Michio Masuda ,  Yasufumi Yumde

发明人： Masaharu Kobayashi ,  Takaharu Noguchi ,  Takao Arai ,  Michio Masuda ,  Yasufumi Yumde

IPC分类号： G11B20/12 ,  G11B5/008 ,  G11B5/09 ,  G11B5/53 ,  G11B20/10 ,  G11B20/18 ,  H04N5/7826 ,  H04N5/926 ,  H04N9/806 ,  H04N9/79 ,  H04N5/782

CPC分类号： H04N5/78263 ,  G11B20/10527 ,  G11B20/1809 ,  G11B5/0086 ,  G11B5/00865 ,  G11B5/531 ,  H04N5/926 ,  H04N5/9268 ,  H04N9/8063

摘要： The recording area of the magnetic tape is divided into a first area for recording a PCM converted audio signal and a second area for recording a PCM converted video information. In recording the audio signal and the video information which have been separately PCM converted, the magnetic tape is wrapped around the rotary heads so that a wrap angle of each of said first and second areas is less than 90.degree. with respect to the rotary heads of a predetermined diameter.

摘要翻译： 磁带的记录区域被分成用于记录PCM转换的音频信号的第一区域和用于记录PCM转换的视频信息的第二区域。 在记录已经单独PCM转换的音频信号和视频信息时，磁带被卷绕在旋转磁头上，使得所述第一和第二区域中的每一个的包角相对于旋转磁头的旋转磁头小于90度 预定直径。

公开(公告)号：US4646301A

公开(公告)日：1987-02-24

申请号：US665378

申请日：1984-10-26

申请人： Hiroo Okamoto ,  Masaharu Kobayashi ,  Hiroyuki Kimura ,  Takaharu Noguchi ,  Takao Arai

发明人： Hiroo Okamoto ,  Masaharu Kobayashi ,  Hiroyuki Kimura ,  Takaharu Noguchi ,  Takao Arai

IPC分类号： H04L1/00 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/27 ,  H03M13/29

CPC分类号： G11B20/1809 ,  G06F11/10 ,  H03M13/29

摘要： Error correction of digital signals is suited for codes having error detection and correction words, such as doubly-encoded Reed-Solomon code. In a first decoding, at least error detection is effected and flags indicating decoding conditions are added. In a second decoding, error detection for first code blocks and error correction for S2 words at unknown locations and E flagged word erasures, where d1 is a Hamming distance and S2 and E satisfy a relation of 2S2+E.ltoreq.d1-1, are parallely or sequentially effected, and a combination of S2 and E having a high correction capability and a low probability of miscorrection is selected from a plurality of correction results of error locations and the numbers of flags added at the first decoding, and the word errors are corrected based on the selected combination.

摘要翻译： 数字信号的纠错适用于具有错误检测和纠错字的代码，例如双重编码的里德 - 所罗门码。 在第一解码中，至少进行错误检测，并且添加指示解码条件的标志。 在第二解码中，用于第一代码块的错误检测和未知位置处的S2字的错误检测和E标记的字擦除，其中d1是汉明距离，S2和E满足2S2 + E 的关系， 平行或顺序地实现，并且从错误位置的多个校正结果和在第一次解码时添加的标志数量，选择具有高校正能力和低错误概率的S2和E的组合，并且单词错误 根据所选择的组合进行校正。

公开(公告)号：US4646170A

公开(公告)日：1987-02-24

申请号：US757448

申请日：1985-07-22

申请人： Masaharu Kobayashi ,  Hiroo Okamoto ,  Takao Arai

发明人： Masaharu Kobayashi ,  Hiroo Okamoto ,  Takao Arai

IPC分类号： G11B20/12 ,  G11B5/09 ,  G11B20/18 ,  G11B5/02 ,  G06F11/10

CPC分类号： G11B20/1809

摘要： In a stationary head type PCM recorder having an A/D converter for sampling an analog signal and converting the analog signal to a digital signal, a signal processing circuit including data delay means for adding an error detection and correction code and a predetermined signal to the digital signal for each error correction group of a predetermined number of samples, and a multi-track head for recording an output of the signal processing circuit on a plurality of tracks of a magnetic record medium and reproducing the signals recorded on the magnetic record medium; incorrectability of the error detection and correction code for a burst error in the output analog signal due to a burst error in the reproduced output is reduced by delaying parity data by the error detection and correction code and the digital signal data by different delay times such that the digital signal data are dispersely recorded in a track direction and a tape transport direction, and allotting the delayed data to the multi-track head such that the data of the adjacent sample points are spaced from each other by at least the distribution length of the parity data and the parity data is arranged between the distributed adjacent data.

摘要翻译： 在具有用于对模拟信号进行采样并将模拟信号转换为数字信号的A / D转换器的静态磁头型PCM记录器中，包括数据延迟装置的信号处理电路，用于将误差检测和校正码以及预定信号加到 数字信号，以及用于在磁记录介质的多个轨道上记录信号处理电路的输出并再现记录在磁记录介质上的信号的多轨头; 由于错误检测和校正码以及数字信号数据通过不同的延迟时间来延迟奇偶校验数据，所以减少了由于再现输出中的脉冲串错误导致的输出模拟信号中的脉冲串错误的错误检测和校正码的不正确性， 数字信号数据被分散地记录在轨道方向和磁带传输方向上，并且将延迟的数据分配给多磁道磁头，使得相邻采样点的数据彼此间隔至少为 奇偶校验数据和奇偶校验数据被布置在分布的相邻数据之间。

公开(公告)号：US4570153A

公开(公告)日：1986-02-11

申请号：US621744

申请日：1984-06-18

申请人： Masaharu Kobayashi ,  Takao Arai ,  Tsutomu Noda

发明人： Masaharu Kobayashi ,  Takao Arai ,  Tsutomu Noda

IPC分类号： H03M1/12 ,  G11B20/10 ,  H03M1/00 ,  H04B14/02 ,  H04B14/04 ,  H04J3/06

CPC分类号： G11B20/10527 ,  H03M1/1019 ,  H04B14/04 ,  H03M1/504

摘要： A signal conversion apparatus for use in a PCM signal processing system in which a series of multi-bit digital signals is produced through sampling and quantization of a multi-channel analog signal. The series of multi-bit digital signals includes groups of multi-bit digital signals being representative of respective analog signal portions constituting the multi-channel analog signal. The apparatus comprises a translating section for producing substitutional multi-bit digital signals from at least one of the groups of digital signals corresponding to at least one analog signal portion, which substitutional digital signals represent amplitudes of the one analog signal portion at sampling points different from those at which the one analog signal was sampled to provide the one group of digital signals. The substitutional digital signals are substituted, in the translating section, for the one group of the digital signals to produce a corresponding group of sampling point-shifted multi-bit digital signals. The resulting PCM multi-bit digital signals are acceptable by digital-to-analog conversion processor requiring PCM digital signals generated through sampling at shifted or different sampling points as compared with the above-mentioned series of digital signals.

摘要翻译： 一种在PCM信号处理系统中使用的信号转换装置，其中通过多通道模拟信号的采样和量化产生一系列多位数字信号。 多比特数字信号系列包括代表构成多声道模拟信号的相应模拟信号部分的多比特数字信号组。 该装置包括用于从与至少一个模拟信号部分相对应的数字信号组中的至少一个产生替代多位数字信号的转换部分，该替代数字信号表示在不同于的模拟信号部分的采样点处的一个模拟信号部分的振幅 对一个模拟信号进行采样以提供一组数字信号。 替代数字信号在转换部分中代替一组数字信号，以产生相应的采样点移位多位数字信号组。 与上述一系列数字信号相比，所得到的PCM多位数字信号可以通过数模转换处理器来接受，该数模转换处理器需要通过在移位或不同采样点的采样产生的PCM数字信号。

公开(公告)号：US4716567A

公开(公告)日：1987-12-29

申请号：US827606

申请日：1986-02-10

申请人： Masahiro Ito ,  Masaharu Kobayashi ,  Takao Arai

发明人： Masahiro Ito ,  Masaharu Kobayashi ,  Takao Arai

IPC分类号： G11B20/12 ,  G11B20/18 ,  H03M13/27 ,  H04N5/926 ,  G06F11/10

CPC分类号： H03M13/2764 ,  G11B20/1809 ,  H04N5/9267

摘要： In a method of transmitting digital data including the steps of constructing one block by a plurality of digital data, constructing one frame by a plurality of blocks, adding two kinds of mutually different error detection and correction codes to these blocks and transmitting these digital data together with the codes that are added, the digital data are not interleaved, only the error detection and correction codes are interleaved and these interleaved codes are added to the digital data.

摘要翻译： 在发送数字数据的方法中，包括通过多个数字数据构造一个块的步骤，通过多个块构造一个帧，向这些块添加两种相互不同的错误检测和校正码并将这些数字数据一起发送 利用添加的代码，数字数据不被交织，只有错误检测和校正码被交织，并且这些交织的代码被添加到数字数据。