公开(公告)号：US20120218802A1

公开(公告)日：2012-08-30

申请号：US13403398

申请日：2012-02-23

申请人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

发明人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

IPC分类号： G11C15/02

CPC分类号： G11C15/02 ,  G11C11/161 ,  G11C15/046 ,  H01L27/228

摘要： One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.

摘要翻译： 一个实施例提供一种内容可寻址存储器，包括：一对自旋MOSFET，其包括：第一自旋MOSFET，其磁化状态根据存储的数据设置; 以及第二自旋MOSFET，其磁化状态根据存储的数据设定，第二自旋MOSFET与第一自旋MOSFET并联连接; 第一布线，被配置为施加栅极电压，使得第一自旋MOSFET和第二自旋MOSFET中的任何一个根据搜索数据变为导电; 以及配置为向第一自旋MOSFET和第二自旋MOSFET两者施加电流的第二布线。

公开(公告)号：US20110194342A1

公开(公告)日：2011-08-11

申请号：US12889881

申请日：2010-09-24

申请人： Hideyuki SUGIYAMA ,  Tetsufumi TANAMOTO ,  Takao MARUKAME ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

发明人： Hideyuki SUGIYAMA ,  Tetsufumi TANAMOTO ,  Takao MARUKAME ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

IPC分类号： G11C11/14

CPC分类号： G11C14/0081

摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.

摘要翻译： 某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接 第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括 连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

公开(公告)号：US20100072529A1

公开(公告)日：2010-03-25

申请号：US12565303

申请日：2009-09-23

申请人： Takao MARUKAME ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Yoshiaki SAITO

发明人： Takao MARUKAME ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Yoshiaki SAITO

IPC分类号： H01L29/82 ,  B05D3/02 ,  B32B15/04

CPC分类号： H01L29/66984 ,  H01F10/1936 ,  H01F10/265 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12 ,  Y10T428/12611

摘要： A stack includes a crystalline MgO layer, crystalline Heusler alloy layer, and amorphous Heusler alloy layer. The crystalline Heusler alloy layer is provided on the MgO layer. The amorphous Heusler alloy layer is provided on the crystalline Heusler alloy layer.

摘要翻译： 堆叠包括结晶MgO层，结晶Heusler合金层和非晶Heusler合金层。 结晶Heusler合金层设置在MgO层上。 非晶Heusler合金层设置在结晶Heusler合金层上。

公开(公告)号：US20120250399A1

公开(公告)日：2012-10-04

申请号：US13403308

申请日：2012-02-23

申请人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

发明人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

IPC分类号： G11C11/16 ,  H03K19/177

CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

公开(公告)号：US20100072528A1

公开(公告)日：2010-03-25

申请号：US12561475

申请日：2009-09-17

申请人： Tomoaki INOKUCHI ,  Takao Marukame ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

发明人： Tomoaki INOKUCHI ,  Takao Marukame ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

IPC分类号： H01L29/82

CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： A spin transistor includes a first ferromagnetic layer, a second ferromagnetic layer, a semiconductor layer between the first and second ferromagnetic layers, and a gate electrode on or above a surface of the semiconductor layer, the surface being between the first and second ferromagnetic layers. The first ferromagnetic layer comprises a ferromagnet which has a first minority spin band located at a high energy side and a second minority spin band located at a low energy side, and has a Fermi level in an area of the high energy side higher than a middle of a gap between the first and second minority spin bands.

摘要翻译： 自旋晶体管包括第一铁磁层，第二铁磁层，第一和第二铁磁层之间的半导体层，以及在半导体层的表面上或上方的栅电极，该表面位于第一和第二铁磁层之间。 第一铁磁层包括具有位于高能侧的第一少数自旋带和位于低能侧的第二少数自旋带的铁磁体，并且在高能量侧的区域中的费米能级高于中间 第一和第二少数自旋带之间的间隙。

公开(公告)号：US20090179667A1

公开(公告)日：2009-07-16

申请号：US12339638

申请日：2008-12-19

申请人： Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO ,  Tetsufumi TANAMOTO

发明人： Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO ,  Tetsufumi TANAMOTO

IPC分类号： H03K19/094 ,  H03K19/173

CPC分类号： H03K19/1733 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1697

摘要： It is made possible to provide a reconfigurable logic circuit with which high integration can be achieved. A reconfigurable logic circuit includes: a multiplexer which includes a plurality of spin MOSFETs each having a source and drain containing a magnetic material, and a selecting portion including a plurality of MOSFETs and selecting a spin MOSFET from the plurality of spin MOSFETs, based on control data transmitted from control lines; a determining circuit which determines whether magnetization of the magnetic material of the source and drain of a selected spin MOSFET, which is selected by the selecting portion, is in a first state or in a second state; and a first and second write circuits which put the magnetization of the magnetic material of the source and drain of the selected spin MOSFET into the second and first states respectively by supplying a write current flowing between the source and drain of the selected spin MOSFET.

摘要翻译： 可以提供可实现高集成度的可重构逻辑电路。 可重配置逻辑电路包括：多路复用器，其包括多个自旋MOSFET，每个具有包含磁性材料的源极和漏极，以及包括多个MOSFET的选择部分，并且基于控制从多个自旋MOSFET中选择自旋MOSFET 从控制线传输的数据; 确定电路，其确定由选择部分选择的所选择的自旋MOSFET的源极和漏极的磁性材料的磁化是处于第一状态还是处于第二状态; 以及第一和第二写入电路，其通过提供在选定的自旋MOSFET的源极和漏极之间流动的写入电流，将所选自旋MOSFET的源极和漏极的磁性材料的磁化分别置于第二和第一状态。

公开(公告)号：US20090059659A1

公开(公告)日：2009-03-05

申请号：US12200169

申请日：2008-08-28

申请人： Tomoaki INOKUCHI ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

发明人： Tomoaki INOKUCHI ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

IPC分类号： G11C11/00 ,  H01L29/51 ,  H01L29/82

CPC分类号： H01L29/66984 ,  B82Y25/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3286

摘要： A spin transistor includes a first ferromagnetic layer provided on a substrate and having an invariable magnetization direction, a second ferromagnetic layer provided on the substrate apart from the first ferromagnetic layer in a first direction, and having a variable magnetization direction, a plurality of projecting semiconductor layers provided on the substrate to extend in the first direction, and sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a plurality of channel regions respectively provided in the projecting semiconductor layers, and a gate electrode provided on the channel regions.

摘要翻译： 自旋晶体管包括设置在基板上并具有不变磁化方向的第一铁磁层，在第一方向上设置在与第一铁磁层隔开的基板上并具有可变磁化方向的第二铁磁层，多个突出半导体 设置在基板上以在第一方向上延伸并夹在第一铁磁层和第二铁磁层之间的层，分别设置在突出半导体层中的多个沟道区和设置在沟道区上的栅电极。

公开(公告)号：US20090243653A1

公开(公告)日：2009-10-01

申请号：US12408953

申请日：2009-03-23

申请人： Tomoaki INOKUCHI ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

发明人： Tomoaki INOKUCHI ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

IPC分类号： H03K19/173 ,  G11C11/14

CPC分类号： G11C14/0081 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/02 ,  G11C2213/31 ,  G11C2213/32 ,  H03K19/0944 ,  H03K19/18

摘要： A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET.

摘要翻译： 半导体集成电路包括包括磁性隧道结和磁半导体结之一的n沟道自旋FET，所述n沟道自旋FET包括用于接收输入信号的栅极端子，用于接收第一电源的源极端子 电位和连接到输出端的漏极端子，包括用于接收时钟信号的栅极端子的p沟道FET，用于接收第二电源电位的源极端子和连接到输出端子的漏极端子，后续 连接到输出端子的电路，以及控制电路，其导通p沟道FET以开始对输出端子充电，然后关闭p沟道FET以结束充电，并将输入信号提供给 n沟道自旋FET。

公开(公告)号：US20080239930A1

公开(公告)日：2008-10-02

申请号：US12029117

申请日：2008-02-11

申请人： Yoshiaki SAITO ,  Hideyuki SUGIYAMA ,  Tomoaki INOKUCHI

发明人： Yoshiaki SAITO ,  Hideyuki SUGIYAMA ,  Tomoaki INOKUCHI

IPC分类号： G11B9/00

CPC分类号： G01R33/093 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/16 ,  H01L27/228 ,  H01L29/66984 ,  H01L29/7881 ,  H01L43/08

摘要： A spin FET includes a first ferromagnetic film disposed on a first source/drain area, a direction of magnetization thereof being fixed in an upward direction or a downward direction perpendicular to a film surface, a second ferromagnetic film disposed on a second source/drain area, a direction of magnetization thereof being changed in the upward direction or the downward direction, an anti-ferromagnetic ferroelectric film disposed on the second ferromagnetic film, and a tunnel barrier film disposed at least between the first source/drain area and the first ferromagnetic film or between the second source/drain and the second ferromagnetic film. Resistance of the anti-ferromagnetic ferroelectric film is larger than ON resistance when the first and second source/drain areas conduct electricity through the channel area.

摘要翻译： 自旋FET包括设置在第一源/漏区上的第一铁磁膜，其磁化方向沿垂直于膜表面的向上方向或向下方向固定，第二铁磁膜设置在第二源/漏区 其磁化方向在向上方向或向下方向上变化，设置在第二铁磁性膜上的反铁磁性铁电体膜和至少设置在第一源极/漏极区域与第一铁磁性膜之间的隧道势垒膜 或者在第二源极/漏极和第二铁磁膜之间。 当第一和第二源极/漏极区域通过沟道区域导电时，反铁磁铁电体膜的电阻大于导通电阻。

公开(公告)号：US20080062580A1

公开(公告)日：2008-03-13

申请号：US11846040

申请日：2007-08-28

申请人： Tomoaki INOKUCHI ,  Yoshiaki Saito ,  Hideyuki Sugiyama

发明人： Tomoaki INOKUCHI ,  Yoshiaki Saito ,  Hideyuki Sugiyama

IPC分类号： G11B5/33

CPC分类号： G01R33/093 ,  B82Y25/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228 ,  H01L29/66984

摘要： A spin memory includes a magneto-resistance element having a first ferromagnetic layer in which a magnetization direction is pinned, a second ferromagnetic layer in which a magnetization direction changes, and a first nonmagnetic layer between the first and second ferromagnetic layers, a lower electrode and an upper electrode extending in a direction between 45 degrees and 90 degrees relative to an axis of hard magnetization of the second ferromagnetic layer, and sandwiching the magneto-resistance element at one end in a longitudinal direction, a switching element connected to another end in a longitudinal direction of the lower electrode, and a bit line connected to another end in a longitudinal direction of the upper electrode, wherein writing is carried out by supplying spin-polarized electrons to the second ferromagnetic layer and applying a magnetic field from the lower electrode and the upper electrode to the second ferromagnetic layer.

摘要翻译： 自旋存储器包括磁阻元件，其具有其中磁化方向被钉扎的第一铁磁层，磁化方向改变的第二铁磁层和第一和第二铁磁层之间的第一非磁性层，下电极和 相对于第二铁磁层的硬磁化轴在45度和90度之间的方向延伸的上电极，并且在纵向方向的一端夹着磁阻元件，开关元件连接到另一端 下电极的纵向方向和与上电极的纵向方向上的另一端连接的位线，其中通过向第二铁磁层提供自旋极化电子并从下电极施加磁场来进行写入，以及 上电极到第二铁磁层。