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    MEMORY CIRCUIT USING SPIN MOSFETS, PATH TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, SWITCHING BOX CIRCUIT, SWITCHING BLOCK CIRCUIT, AND FIELD PROGRAMMABLE GATE ARRAY
    1.
    发明申请
    MEMORY CIRCUIT USING SPIN MOSFETS, PATH TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, SWITCHING BOX CIRCUIT, SWITCHING BLOCK CIRCUIT, AND FIELD PROGRAMMABLE GATE ARRAY 有权
    使用旋转MOSFET的存储器电路，具有存储器功能的路径晶体管电路，开关盒电路，开关块电路和现场可编程门阵列

    公开(公告)号：US20120250399A1

    公开(公告)日：2012-10-04

    申请号：US13403308

    申请日：2012-02-23

    申请人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

    发明人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

    IPC分类号： G11C11/16 ,  H03K19/177

    CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

    摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

    NONVOLATILE MEMORY CIRCUIT USING SPIN MOS TRANSISTORS
    2.
    发明申请
    NONVOLATILE MEMORY CIRCUIT USING SPIN MOS TRANSISTORS 有权
    使用旋转MOS晶体管的非易失性存储器电路

    公开(公告)号：US20110194342A1

    公开(公告)日：2011-08-11

    申请号：US12889881

    申请日：2010-09-24

    申请人： Hideyuki SUGIYAMA ,  Tetsufumi TANAMOTO ,  Takao MARUKAME ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

    发明人： Hideyuki SUGIYAMA ,  Tetsufumi TANAMOTO ,  Takao MARUKAME ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

    IPC分类号： G11C11/14

    CPC分类号： G11C14/0081

    摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.

    摘要翻译： 某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接 第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括 连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120168838A1

    公开(公告)日：2012-07-05

    申请号：US13419947

    申请日：2012-03-14

    申请人： Takao MARUKAME ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    发明人： Takao MARUKAME ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/66984 ,  H01L21/823814 ,  H01L21/84 ,  H01L21/845 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/49 ,  H01L29/66075

    摘要： A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.

    摘要翻译： 根据实施例的半导体器件包括：半导体层; 半导体层中的源极和漏极区域; 在源极和漏极区域中的每一个上的磁性金属半导体化合物膜，包括与半导体层的半导体相同的半导体的磁性金属半导体化合物膜和磁性金属; 源极区域和漏极区域之间的半导体层上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 栅极侧壁，其形成在所述栅电极的侧部，所述栅极侧壁由绝缘材料制成; 在所述源极和漏极区域中的每一个上形成在所述磁性金属半导体化合物膜上的膜堆叠，所述膜堆叠包括磁性层; 以及形成在栅极侧壁上的氧化物层，所述氧化物层包含与膜堆叠中的元件相同的元件。

    CONTENT ADDRESSABLE MEMORY
    5.
    发明申请
    CONTENT ADDRESSABLE MEMORY 失效
    内容可寻址内存

    公开(公告)号：US20120218802A1

    公开(公告)日：2012-08-30

    申请号：US13403398

    申请日：2012-02-23

    申请人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

    发明人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

    IPC分类号： G11C15/02

    CPC分类号： G11C15/02 ,  G11C11/161 ,  G11C15/046 ,  H01L27/228

    摘要： One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.

    摘要翻译： 一个实施例提供一种内容可寻址存储器，包括：一对自旋MOSFET，其包括：第一自旋MOSFET，其磁化状态根据存储的数据设置; 以及第二自旋MOSFET，其磁化状态根据存储的数据设定，第二自旋MOSFET与第一自旋MOSFET并联连接; 第一布线，被配置为施加栅极电压，使得第一自旋MOSFET和第二自旋MOSFET中的任何一个根据搜索数据变为导电; 以及配置为向第一自旋MOSFET和第二自旋MOSFET两者施加电流的第二布线。

    ANALOG-TO-DIGITAL CONVERTER
    7.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER 失效
    模拟数字转换器

    公开(公告)号：US20130076551A1

    公开(公告)日：2013-03-28

    申请号：US13535118

    申请日：2012-06-27

    申请人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    发明人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    IPC分类号： H03M1/36

    CPC分类号： H03M1/1061 ,  H03F3/45183 ,  H03F2203/45391 ,  H03F2203/45392 ,  H03F2203/45674 ,  H03K5/2481 ,  H03M1/365

    摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.

    摘要翻译： 根据实施例，模数转换器包括产生比较电压的电压产生单元; 和比较者。 每个比较器将比较电压中的任何一个与模拟输入电压进行比较，并输出数字信号。 每个比较器包括用于检测两个输入之间的电位差的差分对电路。 差分对电路包括第一和第二电路部分。 第一电路部分包括具有一个输入端的栅极的第一晶体管; 以及与第一晶体管串联连接的电阻器。 第二电路部分包括第二晶体管，其具有提供另一输入的栅极，并与第一晶体管形成差分对; 以及与第二晶体管串联连接的可变电阻器。 可变电阻器包括可变电阻元件，每个电阻元件具有根据控制信号可变地设置的电阻值。

    ANALOG-TO-DIGITAL CONVERTER
    8.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER 失效
    模拟数字转换器

    公开(公告)号：US20130076550A1

    公开(公告)日：2013-03-28

    申请号：US13536085

    申请日：2012-06-28

    申请人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    发明人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    IPC分类号： H03M1/34

    CPC分类号： H03M1/1061 ,  H01L27/22 ,  H01L43/08 ,  H03M1/365

    摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.

    摘要翻译： 根据实施例，模数转换器包括电压产生单元和多个比较器。 电压产生单元被配置为通过多个可变电阻器分压参考电压以产生多个比较电压。 多个比较器中的每一个被配置为将多个比较电压中的任何一个与模拟输入电压进行比较，并且基于比较电压和模拟输入电压之间的比较结果输出数字信号。 多个可变电阻器中的每一个包括串联连接的多个可变电阻元件，并且多个可变电阻元件中的每一个具有根据外部信号可变地设置的电阻值。

    INCOMING CIRCUIT USING MAGNETIC RESONANT COUPLING
    9.
    发明申请
    INCOMING CIRCUIT USING MAGNETIC RESONANT COUPLING 审中-公开
    使用磁共振耦合电路

    公开(公告)号：US20130069440A1

    公开(公告)日：2013-03-21

    申请号：US13537144

    申请日：2012-06-29

    申请人： Takao MARUKAME ,  Hirotaka NISHINO ,  Masamichi SUZUKI ,  Atsuhiro KINOSHITA

    发明人： Takao MARUKAME ,  Hirotaka NISHINO ,  Masamichi SUZUKI ,  Atsuhiro KINOSHITA

    IPC分类号： H02J17/00

    CPC分类号： H02J50/12 ,  H02J17/00

    摘要： According to one embodiment, an incoming circuit using a magnetic resonant coupling includes an incoming coil which receives magnetic field energy transmitted from an outgoing coil under conditions of energy power transmission by the magnetic resonant coupling, and an incoming circuit which comprises a variable capacitor and a rectifier circuit and which outputs, as a direct-current voltage, the magnetic field energy received by the incoming coil. A capacitance of the variable capacitor is automatically controlled to change in an analog form along with the change of the direct-current voltage and to keep the transmission efficiency of the magnetic field energy at a fixed value by directly feeding back the direct-current voltage to the variable capacitor.

    摘要翻译： 根据一个实施例，使用磁共振耦合的输入电路包括输入线圈，其在由磁共振耦合的能量功率传输的条件下接收从输出线圈传输的磁场能量，以及输入电路，其包括可变电容器和 整流电路，其输出由输入线圈接收的磁场能量作为直流电压。 随着直流电压的变化，可变电容器的电容被自动控制为模拟形式的变化，并且通过将直流电压直接反馈到直流电压来保持磁场能量的传输效率为固定值 可变电容器。

    MEMORY SYSTEM INCLUDING KEY-VALUE STORE
    10.
    发明申请
    MEMORY SYSTEM INCLUDING KEY-VALUE STORE 有权

    公开(公告)号：US20130042060A1

    公开(公告)日：2013-02-14

    申请号：US13569605

    申请日：2012-08-08

    申请人： Takao MARUKAME ,  Atsuhiro Kinoshita ,  Kosuke Tatsumura

    发明人： Takao MARUKAME ,  Atsuhiro Kinoshita ,  Kosuke Tatsumura

    IPC分类号： G06F12/00

    CPC分类号： G06F17/30982 ,  G06F12/0246 ,  G06F17/30097 ,  G06F17/3012 ,  G06F2212/7201

    摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.