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公开(公告)号：US20130093019A1
公开(公告)日：2013-04-18
申请号：US13272409
申请日：2011-10-13
申请人： Takashi ANDO , Josephine B. CHANG , Sivananda K. KANAKASABAPATHY , Pranita KULKARNI , Theodorus E. STANDAERT , Tenko YAMASHITA
发明人： Takashi ANDO , Josephine B. CHANG , Sivananda K. KANAKASABAPATHY , Pranita KULKARNI , Theodorus E. STANDAERT , Tenko YAMASHITA
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66803 , H01L29/785
摘要： A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed.
摘要翻译： 晶体管，例如FinFET，包括设置在衬底上的栅极结构。 栅极结构具有宽度以及限定栅极结构的两个相对侧壁的长度和高度。 晶体管还包括通过栅极结构的侧壁的源极区域和漏极区域之间的至少一个导电沟道; 设置在所述栅极结构上方的电介质层和在所述栅极结构外部的所述导电沟道的部分; 以及介电层下面的气隙。 气隙设置成与栅极结构的侧壁相邻，并且用于减小晶体管的寄生电容。 还公开了制造晶体管的至少一种方法。
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2.发明申请METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN 审中-公开用于制作具有残留通道和放大源/漏极的晶体管的方法公开(公告)号：US20130178022A1
公开(公告)日：2013-07-11
申请号：US13618186
申请日：2012-09-14
申请人： Kangguo CHENG , Ali KHAKIFIROOZ , Sivananda KANAKASABAPATHY , Pranita KULKARNI , Balasubramanian S. HARAN
发明人： Kangguo CHENG , Ali KHAKIFIROOZ , Sivananda KANAKASABAPATHY , Pranita KULKARNI , Balasubramanian S. HARAN
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/7848 , H01L29/785
摘要： A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer.
摘要翻译： 提供了一种用于制造晶体管的方法。 根据该方法，在第一半导体层上形成第二半导体层，在第二半导体层上形成虚拟栅极结构。 栅极间隔件形成在虚拟栅极结构的侧壁上，并且去除虚拟栅极结构以形成空腔。 除去腔下方的第二半导体层。 栅电介质形成在第一半导体层的第一部分上并且邻近第二半导体层的侧壁和栅极间隔物的侧壁。 栅极导体形成在栅极电介质的第一部分上并邻接栅极电介质的第二部分。 凸起的源/漏区形成在第二半导体层中，其中至少部分凸起的源极/漏极区在栅极间隔物之下。
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公开(公告)号：US20130078777A1
公开(公告)日：2013-03-28
申请号：US13618054
申请日：2012-09-14
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/1203 , H01L29/78654 , H01L29/78696
摘要： A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type.
摘要翻译： 提供了一种用于制造晶体管的方法。 根据该方法，在半导体层上形成掺杂材料层，掺杂剂从掺杂材料层扩散到半导体层中，以在半导体层中形成渐变掺杂区域。 渐变掺杂区域在半导体层的顶表面附近具有更高的掺杂浓度，并且在半导体层的底表面附近具有较低的掺杂浓度，掺杂浓度逐渐降低。 去除掺杂材料层，然后在半导体层上形成栅叠层。 源极和漏极区域形成在栅极堆叠下方的半导体层中的有源区域附近。 有源区域包括渐变掺杂区域的至少一部分，源极和漏极区域以及有源区域具有相同的导电类型。
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公开(公告)号：US20130175606A1
公开(公告)日：2013-07-11
申请号：US13344806
申请日：2012-01-06
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66515 , H01L21/28518 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L23/485 , H01L27/0883 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
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公开(公告)号：US20120216158A1
公开(公告)日：2012-08-23
申请号：US13457932
申请日：2012-04-27
申请人： Stephen W. BEDELL , Kangguo CHENG , Bruce B. DORIS , Ali KHAKIFIROOZ , Pranita KULKARNI , Katherine L. SAENGER
发明人： Stephen W. BEDELL , Kangguo CHENG , Bruce B. DORIS , Ali KHAKIFIROOZ , Pranita KULKARNI , Katherine L. SAENGER
CPC分类号： H01L21/84 , H01L21/823807
摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.
摘要翻译： 应变Si和应变SiGe绝缘体器件，制造方法和设计结构。 该方法包括在绝缘体上硅晶片上生长SiGe层。 该方法还包括将SiGe层图案化成PFET和NFET区域，使得PFET和NFET区域中的SiGe层中的应变被放宽。 该方法还包括通过离子注入直接在SiGe层下面的Si层的至少一部分而非晶化。 该方法还包括进行热退火以使Si层重结晶，使得晶格常数与弛豫SiGe的晶格常数相匹配，从而在NFET区域上产生拉伸应变。 该方法还包括从NFET区域去除SiGe层。 该方法还包括执行Ge工艺以将PFET区域中的Si层转换为压缩应变的SiGe。
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公开(公告)号：US20120313168A1
公开(公告)日：2012-12-13
申请号：US13155878
申请日：2011-06-08
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.
摘要翻译： 极薄的绝缘体上硅晶体管包括在衬底上方的掩埋氧化物层。 掩埋氧化物层例如具有小于50nm的厚度。 硅层在掩埋氧化物层之上。 硅层上的栅极叠层包括至少形成在硅层上的栅极电介质和形成在栅极电介质上的栅极导体。 栅极间隔物在硅层上具有第一部分，第二部分邻近栅极堆叠。 第一升高的源极/漏极区域和第二升高的源极/漏极区域各自具有包括硅层的一部分的第一部分和与栅极间隔物相邻的第二部分。 至少部分地在衬底内形成至少一个嵌入式应力器，其在硅层中形成的硅沟道区域上施加预定的应力。
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7.发明申请RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER 有权从应力衬里增强应变耦合的提高源/排水结构公开(公告)号：US20120299103A1
公开(公告)日：2012-11-29
申请号：US13570833
申请日：2012-08-09
IPC分类号： H01L29/06
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译： 提供一种晶体管，其包括衬底上方的掩埋氧化物层。 硅层在掩埋氧化物层之上。 栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。 氮化物衬垫与栅堆叠相邻。 氧化物衬垫与氮化物衬垫相邻。 一组具有包括硅层的一部分的部分的凸起的源/漏区。 所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。
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公开(公告)号：US20130062702A1
公开(公告)日：2013-03-14
申请号：US13227750
申请日：2011-09-08
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/51 , H01L21/28176 , H01L21/823857 , H01L21/823864 , H01L29/49 , H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/7833
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.
摘要翻译： 形成具有多个阈值电压器件的互补金属氧化物半导体（CMOS）结构的方法包括在半导体衬底上形成第一晶体管器件和第二晶体管器件。 第一晶体管器件和第二晶体管器件最初具有牺牲性虚拟栅极结构。 去除牺牲虚拟栅极结构，并且为第一晶体管器件选择性地形成一组垂直氧化物间隔物。 垂直氧化物间隔物组与第一晶体管器件的栅介质层直接接触，使得第一晶体管器件相对于第二晶体管器件具有偏移的阈值电压。
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9.发明申请RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER 有权从应力衬里增强应变耦合的提高源/排水结构公开(公告)号：US20130011975A1
公开(公告)日：2013-01-10
申请号：US13614572
申请日：2012-09-13
IPC分类号： H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer.
摘要翻译： 栅极堆叠形成在掩埋氧化物层上方的硅层上。 栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。 在硅层和栅叠层上形成第一氮化物层。 在第一氮化物层上形成氧化物层。 在氧化物层上形成第二氮化物层。 蚀刻第一氮化物层和氧化物层，以便形成氮化物衬垫和邻近栅叠层的氧化物衬垫。 蚀刻第二氮化物层以形成邻近氧化物衬垫的第一氮化物间隔物。 与氮化物衬垫，氧化物衬垫和第一氮化物间隔物相邻地外延形成刻面隆起的源极/漏极区。 使用第一氮化物间隔物将离子植入到刻面隆起的源极/漏极区域中。
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公开(公告)号：US20120302020A1
公开(公告)日：2012-11-29
申请号：US13568580
申请日：2012-08-07
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
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