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    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    1.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    半导体器件的制造方法

    公开(公告)号：US20060270121A1

    公开(公告)日：2006-11-30

    申请号：US11381657

    申请日：2006-05-04

    申请人： Takashi Ipposhi ,  Katsuyuki Horita ,  Shigeto Maegawa

    发明人： Takashi Ipposhi ,  Katsuyuki Horita ,  Shigeto Maegawa

    IPC分类号： H01L21/84

    CPC分类号： H01L21/76283

    摘要： Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant. Then, after removing the resist and depositing an isolation oxide film on the whole surface, an isolation oxide film is flattened in good thickness precision in the height specified by the thickness of a silicon nitride film by performing CMP treatment which used the silicon nitride film as the polishing stopper.

    摘要翻译： 即使制造使用部分和全部隔离组合使用技术进行元件隔离的绝缘隔离结构，也可以制造半导体器件的制造方法，该半导体器件可以制造半导体器件，其特征在于SOI层中形成绝缘隔离 获得了。 通过使用图案化的抗蚀剂和沟槽掩模作为掩模来进行内壁氧化膜和SOI层的蚀刻，形成穿透SOI层并到达嵌入绝缘层的完全隔离用沟槽。 此时，由于去除了在上部没有形成抗蚀剂的CVD氧化膜的一部分，由于氮化硅膜被CVD氧化膜保护，所以氮化硅膜的厚度保持恒定。 然后，在除去抗蚀剂并在整个表面上沉积隔离氧化物膜之后，通过进行使用氮化硅膜的CMP处理将隔离氧化物膜以由氮化硅膜的厚度规定的高度精确地平坦化，使用氮化硅膜作为 抛光止动器。

    Semiconductor device, method of manufacturing same and method of designing same
    4.
    发明授权
    Semiconductor device, method of manufacturing same and method of designing same 失效
    半导体装置及其制造方法及其设计方法

    公开(公告)号：US06953979B1

    公开(公告)日：2005-10-11

    申请号：US09466934

    申请日：1999-12-20

    申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

    摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

    Semiconductor memory device and method of manufacturing the same
    9.
    发明申请
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US20050078546A1

    公开(公告)日：2005-04-14

    申请号：US10927638

    申请日：2004-08-27

    申请人： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  koji Nii

    发明人： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  koji Nii

    IPC分类号： H01L27/11 ,  G11C8/02 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  Y10S257/903 ,  Y10S257/904

    摘要： A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

    摘要翻译： 连接到字线的触点形成在SRAM单元的存取晶体管的栅电极上。 接触通过元件隔离绝缘膜以达到SOI层。 驱动晶体管的体区和存取晶体管的体区通过位于元件隔离绝缘膜下方的SOI层彼此电连接。 因此，存取晶体管是具有通过触点与主体区域连接的栅电极的DTMOS结构，该触点又电连接到驱动晶体管的体区。 因此，可以在抑制用于形成SRAM单元的区域的增加的同时稳定操作。

    Semiconductor device having an SOI structure, manufacturing method thereof, and memory circuit
    10.
    发明授权
    Semiconductor device having an SOI structure, manufacturing method thereof, and memory circuit 有权
    具有SOI结构的半导体器件，其制造方法和存储电路

    公开(公告)号：US08067804B2

    公开(公告)日：2011-11-29

    申请号：US11251911

    申请日：2005-10-18

    申请人： Shigeto Maegawa ,  Takashi Ipposhi

    发明人： Shigeto Maegawa ,  Takashi Ipposhi

    IPC分类号： H01L29/786

    CPC分类号： H01L29/78621 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/78615 ,  H01L29/78624

    摘要： The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer. The semiconductor layer has a body region of a first conduction type, a source region of a second conduction type and a drain region of the second conduction type, and a gate electrode is formed on the body region between the source region and the drain region via a gate oxide film. The source region includes an extension layer of the second conduction type, and a silicide layer which makes contact with the extension layer at its side face, and a crystal defect region is formed on a region of a depletion layer generated in a boundary portion between the silicide layer and the body region.

    摘要翻译： 本发明提供能够抑制身体浮动效应的半导体器件及其制造方法。 具有SOI结构的半导体器件包括硅衬底，形成在硅衬底上的掩埋绝缘层和形成在掩埋绝缘层上的半导体层。 半导体层具有第一导电类型的主体区域，第二导电类型的源极区域和第二导电类型的漏极区域，并且栅极电极形成在源极区域和漏极区域通孔之间的体区域上 栅氧化膜。 源极区域包括第二导电类型的延伸层和在其侧面与延伸层接触的硅化物层，并且在位于第二导电类型之间的边界部分中产生的耗尽层的区域上形成晶体缺陷区域 硅化物层和身体区域。