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33 条记录 (耗时 0.032 秒)

    Semiconductor integrated circuit having a plurality of oscillation circuits
    1.
    发明授权
    Semiconductor integrated circuit having a plurality of oscillation circuits 失效
    具有多个振荡电路的半导体集成电路

    公开(公告)号：US5261082A

    公开(公告)日：1993-11-09

    申请号：US651098

    申请日：1991-02-04

    申请人： Takashi Ito ,  Kenichi Ishibashi ,  Kenzo Funatsu ,  Naoki Yashiki ,  Katsumi Iwata

    发明人： Takashi Ito ,  Kenichi Ishibashi ,  Kenzo Funatsu ,  Naoki Yashiki ,  Katsumi Iwata

    IPC分类号： G06F1/08 ,  G06F1/04

    CPC分类号： G06F1/08

    摘要： Operation of a clock generating circuit is stopped when the oscillation signals to be selectively transmitted to the clock generating circuit via a multiplexer are switched. The oscillation signals are generated by a first oscillation circuit at a relatively high frequency and by a second oscillation circuit which steadily oscillates at a relatively low frequency. The clock generating operation is resumed in synchronization with the switched oscillation signals.

    摘要翻译： 当通过多路复用器选择性地发送到时钟发生电路的振荡信号被切换时，停止时钟发生电路的操作。 振荡信号由相对高频率的第一振荡电路和以较低频率稳定振荡的第二振荡电路产生。 与切换的振荡信号同步地恢复时钟产生操作。

    ELECTRIC WIRE OR CABLE
    3.
    发明申请
    ELECTRIC WIRE OR CABLE 有权
    电线或电缆

    公开(公告)号：US20120118607A1

    公开(公告)日：2012-05-17

    申请号：US13382506

    申请日：2010-07-06

    申请人： Kenichi Ishibashi ,  Kazumi Mochizuki ,  Yasunobu Kondo

    发明人： Kenichi Ishibashi ,  Kazumi Mochizuki ,  Yasunobu Kondo

    IPC分类号： H01B5/00 ,  B21C1/00

    CPC分类号： H01B1/023 ,  C22C21/00 ,  C22C21/02 ,  C22C21/06 ,  C22C21/08 ,  C22C21/12 ,  C22C21/14 ,  C22C21/16 ,  C22F1/04

    摘要： There is provided an aluminum-alloy material having sufficient electric conductivity and tensile strength as a wiring material and excellent in wire-drawing property, and an electric wire or cable using the same. An electric wire or cable includes an aluminum-alloy strand formed of an aluminum-alloy including Fe: 0.1% by mass or more to less than 1.0% by mass, Zr: 0 to 0.08% by mass, Si: 0.02 to 2.8% by mass, at least one of Cu: 0.05 to 0.63% by mass and Mg: 0.04 to 0.45% by mass, and the remainder being aluminum and unavoidable impurities.

    摘要翻译： 提供具有足够的导电性和拉伸强度的铝合金材料作为布线材料并且拉拔性优良，以及使用该铝合金材料的电线或电缆。 电线或电缆包括由铝合金形成的铝合金线，所述铝合金包含Fe：0.1质量％以上至小于1.0质量％，Zr：0〜0.08质量％，Si：0.02〜2.8质量％ 质量，Cu中的至少一种：0.05〜0.63质量％，Mg：0.04〜0.45质量％，余量为铝和不可避免的杂质。

    Semiconductor integrated circuit system having function of automatically adjusting output resistance value
    5.
    发明授权
    Semiconductor integrated circuit system having function of automatically adjusting output resistance value 失效
    具有自动调节输出电阻值功能的半导体集成电路系统

    公开(公告)号：US06049221A

    公开(公告)日：2000-04-11

    申请号：US111804

    申请日：1998-07-08

    申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

    发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

    IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  H03K19/175

    CPC分类号： H03K19/0005

    摘要： A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.

    摘要翻译： 具有参照正在运行的LSI的温度来自动调整输出电阻值的功能的半导体集成电路系统。 当通过对计时器的输出进行计数而得到的计数值等于预定值时，温度传感器测量LSI的温度。 如果从先前测量值测量的温度波动大于预定宽度，则控制装置发出输出电阻值调整请求信号以输出LSI的电阻调节单元。 当接收到输出电阻值调整请求信号时，输出电阻值调节单元停止LSI之间的信号传输，以输出电阻值与传输线的特性阻抗匹配的方式调整输出电路的输出电阻值 并保持调整后的输出电阻值直到输出电阻值调整单元接收到下一个输出电阻值调整请求信号。

    Method and system for synchronizing data having skew
    6.
    发明授权
    Method and system for synchronizing data having skew 失效
    用于同步具有偏斜的数据的方法和系统

    公开(公告)号：US5867541A

    公开(公告)日：1999-02-02

    申请号：US441613

    申请日：1995-05-15

    申请人： Akira Tanaka ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

    发明人： Akira Tanaka ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

    IPC分类号： G06F13/42 ,  H04L7/00 ,  H04L7/033

    CPC分类号： H04L7/0337 ,  H04L7/0037 ,  H04L7/0008

    摘要： Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.

    摘要翻译： 数据从多个发射机中的任何一个与第一时钟同步发送。 接收机与第一时钟同步地接收数据，第二时钟与第一时钟具有预定的相位关系。 先前在接收机中保持与多个发射机有关的数据接收条件的控制信息，以根据控制信息来控制接收机的接收条件。

    Integrated circuit having function blocks operating in response to clock signals
    9.
    发明授权
    Integrated circuit having function blocks operating in response to clock signals 失效
    具有响应时钟信号工作的功能块的集成电路

    公开(公告)号：US5774702A

    公开(公告)日：1998-06-30

    申请号：US561728

    申请日：1995-11-22

    申请人： Naoki Mitsuishi ,  Kenichi Ishibashi ,  Koichi Hashimura

    发明人： Naoki Mitsuishi ,  Kenichi Ishibashi ,  Koichi Hashimura

    IPC分类号： G06F15/78 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G06F1/06

    CPC分类号： G06F1/08

    摘要： A semiconductor integrated circuit comprising a clock pulse generator, peripheral function blocks and bus master modules. The peripheral function blocks are commonly supplied with a first system clock signal of a constant frequency generated on the basis of the output from the clock pulse generator. The bus master modules are fed with a second system clock signal generated on the basis of the pulse generator output. The frequency of the second system clock signal is variable and lower than that of the first system clock signal. The function blocks supplied with the first system clock signal are connected to a data bus separate from the one connected to the function blocks fed with the second system clock signal.

    摘要翻译： 一种半导体集成电路，包括时钟脉冲发生器，外围功能块和总线主模块。 周边功能块通常被提供有基于来自时钟脉冲发生器的输出而产生的恒定频率的第一系统时钟信号。 总线主模块馈送有基于脉冲发生器输出产生的第二系统时钟信号。 第二系统时钟信号的频率可变并且低于第一系统时钟信号的频率。 与第一系统时钟信号一起提供的功能块连接到与连接到与第二系统时钟信号馈送的功能块相连的数据总线上的数据总线。

    Method and system for controlling cache memory with a storage buffer to increase throughput of a write operation to the cache memory
    10.
    发明授权
    Method and system for controlling cache memory with a storage buffer to increase throughput of a write operation to the cache memory 失效
    用于利用存储缓冲器来控制高速缓冲存储器以增加对高速缓冲存储器的写入操作的吞吐量的方法和系统

    公开(公告)号：US5544340A

    公开(公告)日：1996-08-06

    申请号：US362755

    申请日：1994-12-22

    申请人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

    发明人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0886

    摘要： A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

    摘要翻译： 一种控制设置在CPU和主存储器之间的高速缓冲存储器的方法，其中将要写入高速缓冲存储器的数据和地址对存储在缓冲存储器中。 处理从缓冲存储器读取的多对数据和地址，以比较其地址字段。 基于比较的结果，确定了将数据写入高速缓冲存储器中的写入控制，其被细分为多个存储体。 结果，将多对数据和地址写入高速缓冲存储器的多个组，各对的地址彼此不同。 通过上述规定，可以对高速缓冲存储器的每一组独立地进行写入操作，从而提高写入吞吐量。