公开(公告)号：US07952916B2

公开(公告)日：2011-05-31

申请号：US12366396

申请日：2009-02-05

申请人： Takashi Maeda ,  Yoshihiro Ueda ,  Kenji Tsuchida

发明人： Takashi Maeda ,  Yoshihiro Ueda ,  Kenji Tsuchida

IPC分类号： G11C11/00

CPC分类号： G11C11/1653 ,  G11C11/1673 ,  G11C11/1675

摘要： A resistance-change memory includes first and second bit lines running in the same direction, a third bit line running parallel to the first and second bit lines, fourth and fifth bit lines running in the same direction, a sixth bit line running parallel to the fourth and fifth bit lines, a first memory element which has one and the other terminals connected to the first and third bit lines, and changes to one of first and second resistance states, a first reference element having one and the other terminals connected to the fourth and sixth bit lines, and set in the first resistance state, a second reference element having one and the other terminals connected to the fifth and sixth bit lines, and set in the second resistance state, and a sense amplifier having first and second input terminals connected to the first and fourth bit lines.

摘要翻译： 电阻变化存储器包括沿相同方向运行的第一和第二位线，与第一和第二位线并行运行的第三位线，沿相同方向运行的第四和第五位线，平行于第一位线的第六位线 第四和第五位线，第一存储器元件，其具有连接到第一和第三位线的一个端子和另一个端子，并且改变为第一和第二电阻状态中的一个;第一参考元件，其中一个和另一个端子连接到 第四和第六位线，并且设置在第一电阻状态，第二参考元件，其中一个和另一个端子连接到第五和第六位线，并被设置在第二电阻状态，以及读出放大器，具有第一和第二输入 连接到第一和第四位线的端子。

公开(公告)号：US08189363B2

公开(公告)日：2012-05-29

申请号：US12543793

申请日：2009-08-19

申请人： Kenji Tsuchida ,  Yoshihiro Ueda

发明人： Kenji Tsuchida ,  Yoshihiro Ueda

IPC分类号： G11C11/00 ,  G11C7/02

CPC分类号： G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

摘要： A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit.

摘要翻译： 电阻变化存储器包括两个存储单元阵列，每个存储单元阵列包括多个存储单元，存储单元包括可变电阻元件，分别提供给两个存储单元阵列的两个参考单元阵列，每个参考单元阵列包括多个参考单元， 所述参考单元具有参考值，以及由所述两个存储单元阵列共享的读出放大器，并且通过使用与包括所述存储单元阵列的第一存储单元阵列不同的第二存储单元阵列对应的参考单元阵列来检测所访问的存储器单元中的数据 存取存储单元 在读取数据时，一个参考单元阵列中的特定参考单元总是基于一个存储单元阵列作为单元而被激活用于地址空间。

公开(公告)号：US20070206406A1

公开(公告)日：2007-09-06

申请号：US11673241

申请日：2007-02-09

申请人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

发明人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  Y10S977/935

摘要： A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.

摘要翻译： 自旋注入写入型磁存储器件包括具有磁阻效应元件和选择晶体管的存储单元。 磁阻效应元件的一端连接到第一节点。 选择晶体管具有连接到磁阻效应元件的另一端的第一扩散区域和连接到第二节点的第二扩散区域。 选择线沿着第一方向延伸并连接到选择晶体管的栅电极。 第一互连沿着第二方向延伸并连接到第一节点。 第二互连沿着第二方向延伸并且连接到第二节点。 沿着第一方向相邻的两个存储单元共享第一节点。 沿着第二方向相邻的两个存储单元共享第二节点。

公开(公告)号：US07545672B2

公开(公告)日：2009-06-09

申请号：US11673241

申请日：2007-02-09

申请人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

发明人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  Y10S977/935

摘要： A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.

摘要翻译： 自旋注入写入型磁存储器件包括具有磁阻效应元件和选择晶体管的存储单元。 磁阻效应元件的一端连接到第一节点。 选择晶体管具有连接到磁阻效应元件的另一端的第一扩散区域和连接到第二节点的第二扩散区域。 选择线沿着第一方向延伸并连接到选择晶体管的栅电极。 第一互连沿着第二方向延伸并连接到第一节点。 第二互连沿着第二方向延伸并且连接到第二节点。 沿着第一方向相邻的两个存储单元共享第一节点。 沿着第二方向相邻的两个存储单元共享第二节点。

公开(公告)号：US07457150B2

公开(公告)日：2008-11-25

申请号：US11673206

申请日：2007-02-09

申请人： Kenji Tsuchida ,  Yoshihiro Ueda

发明人： Kenji Tsuchida ,  Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C11/1657 ,  G11C11/1655

摘要： The first memory cell in even columns is composed of a first resistance change element one end of which is connected to a first bit line, and first and second FETs connected in parallel between the other end of the first resistance change element and a second bit line. The second memory cell in odd columns is composed of a second resistance change element one end of which is connected to a third bit line, and third and fourth FETs connected in parallel between the other end of the second resistance change element and a fourth bit line. A gate of the first FET is connected to the first word line. Gates of the second and third FETs are connected together to the second word line. A gate of the fourth FET is connected to the third word line.

摘要翻译： 偶数列中的第一存储单元由第一电阻变化元件组成，其一端连接到第一位线，并且第一和第二FET并联连接在第一电阻变化元件的另一端和第二位线 。 奇数列中的第二存储单元由第二电阻变化元件组成，其一端连接到第三位线，第三和第四FET并联连接在第二电阻变化元件的另一端和第四位线之间 。 第一个FET的栅极连接到第一个字线。 第二和第三FET的栅极连接在一起到第二字线。 第四FET的栅极连接到第三字线。

公开(公告)号：US08514614B2

公开(公告)日：2013-08-20

申请号：US12885175

申请日：2010-09-17

申请人： Takafumi Shimizu ,  Kenji Tsuchida ,  Yoshihiro Ueda

发明人： Takafumi Shimizu ,  Kenji Tsuchida ,  Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1673

摘要： According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to a first direction in a case where an expression of MR ratio ≧|Ic+/Ic−|−1 is satisfied if a critical current of the first direction used to write the magnetoresistive element to the parallel state is set to Ic− and a critical current of a second direction used to write the magnetoresistive element to the anti-parallel state is set to Ic+.

摘要翻译： 根据一个实施例，磁存储器包括磁阻元件，其包括其磁化方向固定的固定层，其磁化方向可变的记录层和设置在固定层和记录层之间的非磁性层。 如果用于将磁阻元件写入平行的第一方向的临界电流满足MR ratio> = | Ic + / Ic- | -1的表达式的情况下，将读取电流的方向设置为第一方向 状态被设定为Ic-，将用于将磁阻元件写入反并联状态的第二方向的临界电流设定为Ic +。

公开(公告)号：US20120155146A1

公开(公告)日：2012-06-21

申请号：US13331229

申请日：2011-12-20

申请人： Yoshihiro UEDA ,  Kenji Tsuchida

发明人： Yoshihiro UEDA ,  Kenji Tsuchida

IPC分类号： G11C11/00

CPC分类号： G11C11/161 ,  G11C11/1659 ,  G11C11/1673

摘要： According to one embodiment, a resistance-change memory includes memory cells between a bit line and a source line, each of the memory cells including a memory element and a cell transistor having a gate connected to a word line, an n-channel transistor having a gate to which a first control voltage is applied, and a current path connected to the bit line, and a p-channel transistor having a gate to which a second control voltage is applied, and a current path connected to the source line. When the memory cell is read, the potential of the bit line is controlled by the first control voltage, and the potential of the source line is controlled by the second control voltage.

摘要翻译： 根据一个实施例，电阻变化存储器包括位线和源极线之间的存储器单元，每个存储器单元包括存储元件和具有连接到字线的栅极的单元晶体管，n沟道晶体管具有 施加第一控制电压的栅极和连接到位线的电流路径，以及具有施加第二控制电压的栅极的p沟道晶体管和连接到源极线的电流路径。 当存储单元被读取时，位线的电位由第一控制电压控制，源极线的电位由第二控制电压控制。

公开(公告)号：US08036015B2

公开(公告)日：2011-10-11

申请号：US12536341

申请日：2009-08-05

申请人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Kiyotaro Itagaki

发明人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Kiyotaro Itagaki

IPC分类号： G11C11/00 ,  G11C7/10

CPC分类号： G11C13/00 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C2013/0054 ,  G11C2213/79

摘要： A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier.

摘要翻译： 电阻存储器包括多个存储单元，具有相互不同的电阻值的多个参考单元，至少一个读出放大器，其具有连接到从多个存储单元中选择的一个选定存储单元的第一输入端， 读取，以及连接到在读取时从多个参考单元中选择的一个选择的参考单元的第二输入端子，以及保持所述至少一个读出放大器的偏移信息的一个锁存电路。 电阻存储器还包括解码器，其根据偏移信息从多个参考单元中选择一个选定的参考单元，并将所选择的一个参考单元连接到至少一个读出放大器的第二输入端。

公开(公告)号：US20110063900A1

公开(公告)日：2011-03-17

申请号：US12885175

申请日：2010-09-17

申请人： Takafumi Shimizu ,  Kenji Tsuchida ,  Yoshihiro Ueda

发明人： Takafumi Shimizu ,  Kenji Tsuchida ,  Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1673

摘要： According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to a first direction in a case where an expression of MR ratio ≧|Ic+/Ic−|−1 is satisfied if a critical current of the first direction used to write the magnetoresistive element to the parallel state is set to Ic− and a critical current of a second direction used to write the magnetoresistive element to the anti-parallel state is set to Ic+.

摘要翻译： 根据一个实施例，磁存储器包括磁阻元件，其包括其磁化方向固定的固定层，其磁化方向可变的记录层和设置在固定层和记录层之间的非磁性层。 如果用于将磁阻元件写入平行状态的第一方向的临界电流满足MR比≧| Ic + / Ic- | -1的表达式的情况下，读取电流的方向被设定为第一方向 被设定为Ic-，将用于将磁阻元件写入反并联状态的第二方向的临界电流设定为Ic +。

公开(公告)号：US08228710B2

公开(公告)日：2012-07-24

申请号：US12715231

申请日：2010-03-01

申请人： Kenji Tsuchida

发明人： Kenji Tsuchida

IPC分类号： G11C11/00

CPC分类号： H01L27/24 ,  G11C8/08 ,  G11C8/10 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  H01L27/228

摘要： A resistance change memory device includes memory cells including two transistors connected in parallel between a first node and a connecting node and a variable resistance element whose one end is connected to the connecting node. The first node of each memory cell and a second node, which is the other end of the variable resistance element of the memory cell, are connected to different bit lines. The first node of a one memory cell and the first node of another memory cell which is adjacent on a first side along the second axis to the one memory are connected to the same bit line. The second node of the one memory cell and the second node of still another memory cell which is adjacent on a second side along the second axis to the one memory cell are connected to the same bit line.

摘要翻译： 电阻变化存储器件包括：存储单元，包括并联连接在第一节点和连接节点之间的两个晶体管，以及可变电阻元件，其一端连接到连接节点。 每个存储单元的第一节点和作为存储单元的可变电阻元件的另一端的第二节点连接到不同的位线。 一个存储单元的第一个节点和另一个存储单元的第一个节点连接到相同的位线，该存储单元的第一个边沿第二个轴与第一个轴相邻。 一个存储单元的第二个节点和另一个存储单元的另一个存储单元的第二个节点连接到相同的位线。